VHDL Code for 4x1 Multiplexer

Find out Test Bench for 4x1 Mux here.

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1_seq is
  
port (
  ip0, ip1, ip2, ip3 : in  std_logic;
  s                  : in  std_logic_vector(0 to 1);
  op                 : out std_logic);
end mux4x1_seq;

architecture beh of mux4x1_seq is

begin  -- beh
p_mux : process (ip0,ip1,ip2,ip3,s)
  variable temp : std_logic;
  begin
    case s is
      when "00" => temp := ip0 ;
      when "01" => temp := ip1;
      when "10" => temp := ip2;
      when others => temp := ip3;
    end case;
    op <= temp;
  end process p_mux;

end beh;