Verilog Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out VHDL Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

module ring_counter(out, clk, rst);
  input clk, rst;
  output reg [3:0] out;
  
always @(posedge clk, posedge rst)
  begin
    if (rst)
      out = 4’b1000;
    else
      out = {out[0];out[3:1]};
  end
endmodule