Rising and Falling Edge Detector using Verilog

 In the real word, there might be many scenario that we need to detect rising edge or falling edge of the signal. If rising/falling edge happens on particular signal, then design can perform certain task. This rising or falling edge can be detected using following code. This code is done in Verilog language. In given below example code, clock clk, input signal sig_a, output rising edge signal ris_a and falling edge signal fal_a are defined. Both ris_a and fal_a are high for one clock cycle when circuit detects rising or falling edge on the sig_a respectively.

//                  ----      ----      ----      ----
//                 |    |    |    |    |    |    |    |
//clk          ----      ----      ----      ----      ----

//                  -------------- 
//                 |              |
//sig_a        ----                -------------------------

//                            -------------- 
//                           |              |
//sig_a_reg    --------------                ----------------

//                  ---------
//                 |         |
//ris_a_reg    ----           --------------------------------

//                                 ---------
//                                |         |
//fal_a_reg    -------------------           -----------------

Above is the graphical representation of all the signals with respect to the clock signal. Basically, sig_a_reg is one clock delayed of sig_a, input signal. The condition to detect rising edge using two signal is that original signal should be high and delayed signal should be low. From above representation, we can see that on the first rising edge of the clock, sig_a is high and delayed version of sig_a, sig_a_reg, is low and we got high on ris_a_reg signal. On the next clock, condition will be false and we will get low on ris_a_reg signal. Same way, to detect falling edge of the signal is that original signal should be low and delayed version of original signal should be high. We can see that fal_a_reg signal is behaving according to the condition.

Given below is the verilog code to detect rising and falling edge.

module ris_fal_edge_det(
input clk,
input sig_a,
output ris_a,
output fal_a);

reg sig_a_reg;
reg ris_a_reg, fal_a_reg;

always @(posedge clk) begin
	sig_a_reg <= sig_a;
	ris_a_reg <= !sig_a_reg &  sig_a;
	fal_a_reg <=  sig_a_reg & !sig_a;
end

assign ris_a = ris_a_reg;
assign fal_a = fal_a_reg;

endmodule