Implement Divide by 2, 4, 8 and 16 Counter using Flip-Flop

Counter plays a very important role into chip designing and verification. It is a very essential part of the VLSI Domain. Whenever we want to design or verify our design, most of the time we require slowing down frequencies. We can suppress this frequency using this counter by 2, 4, 8 or 16 times. Here circuit diagram and verilog code are given below.

Sr. No.	Name of Pin	Direction	Width	Remark
1	Fin	Input	1	Input Signal or Clock Signal
2	F2	Output	1	Divide By 2 Frequency
3	F4	Output	1	Divide By 4 Frequency
4	F8	Output	1	Divide By 8 Frequency
5	F16	Output	1	Divide By 16 Frequency

module divide_by_counter(fin, rst, f2, f4, f8, f16);
 
 input fin, rst;
 output reg f2, f4, f8, f16;
 reg q1, q2, q3, q4;

 always @ (posedge fin, posedge rst)
  begin
   if (rst)
    f2 = 1'b0;
   
   else
   begin 
    q1 = ~f2;
    f2 = q1;
   end
  end

 always @ (posedge q1, posedge rst)
  begin
   if (rst)
    f4 = 1'b0;
   
   else
   begin 
    q2 = ~f4;
    f4 = q2;
   end
  end

  always @ (posedge q2, posedge rst)
  begin
   if (rst)
    f8 = 1'b0;
   
   else
   begin 
    q3 = ~f8;
    f8 = q3;
   end
  end

 always @ (posedge q3, posedge rst)
  begin
   if (rst)
    f16 = 1'b0;
   
   else
   begin 
    q4 = ~f16;
    f16 = q4;
   end
  end

endmodule