Verilog Code for Electronic Combination Lock System using FSM

Sr. No.	Name of Pin	Direction	Width	Description
1	clk	Input	1	Clock Signal
2	rst	Input	1	Reset Signal
3	b0	Input	1	Input Digit “0”
4	b1	Input	1	Input Digit “1”
5	unlock	Output	1	Status for unlock

In this lock system, only two digits are used to unlock system. With the help of "0" and "1", the lock will be unlock but with specific pattern. This lock will be unlock with "01011" code. If this pattern will be identified by lock then lock will be become open and output unlock bit will be "1", otherwise lock remain close and unlock bit will be "0". This Lock System is developed using FSM and there are total six stages.

module electronic_lock(clk,rst,b0,b1,unlock);
 output reg unlock;
 input clk,rst;
 input b0,b1;

 reg [2:0] state;
 reg [2:0] next_state;

 parameter [2:0] s_rst=3'b000;
 parameter [2:0] s1=3'b001;
 parameter [2:0] s2=3'b010;
 parameter [2:0] s3=3'b011;
 parameter [2:0] s4=3'b100;
 parameter [2:0] s5=3'b101;

always @(posedge clk)
 begin
  if (rst)
   state=s_rst;
  else
   state=next_state;
 end

always @(state,b0,b1)
 begin
  case(state)
   s_rst: next_state = b0 ? s1 : b1 ? s_rst : state;
   s1: next_state = b0 ? s1 : b1 ? s2 : state;
   s2: next_state = b0 ? s3 : b1 ? s_rst : state;
   s3: next_state = b0 ? s1 : b1 ? s4 : state;
   s4: next_state = b0 ? s3 : b1 ? s5 : state;
   s5: next_state = b0 ? s1 : b1 ? s_rst : state;
   default: next_state = s_rst;
  endcase
 end

always @(state)
 begin
  case(state)
   s_rst : unlock<=1'b0;
   s1 : unlock<=1'b0;
   s2 : unlock<=1'b0;
   s3 : unlock<=1'b0;
   s4 : unlock<=1'b0;
   s5 : unlock<=1'b1;
   default : unlock<=1'b0;
  endcase
 end

endmodule