Logic Gates with Truth Table in Digital World

Logic gates are basic building blocks of any digital circuits. Logic gates are electronics device that gives output on the different combinations of digital inputs. Different Logic gates are constructed using different technologies depending on different Logic Family like TTL, CMOS, DTL, ECL etc. Logic Circuits include devices such as multiplexers, registers, memory units, processors, which contains more than 100 millions Logic Gates.

There are total six Logic Gates are available

1. AND Gate.
2. OR Gate.
3. NOT Gate.
4. NAND Gate.
5. NOR Gate.
6. EX-OR Gate.
7. EX-NOR Gate.

Verilog Code for Gray Counter

Gray code is one kind of binary number system where only one bit will change at a time. Today gray code is widely used in digital world. This will helpful for error correction and signal transmission. Gray counter is also useful in design and verification in VLSI domain. This code will generate gray code. Find out VHDL Code of Gray Counter here.

Implement Divide by 2, 4, 8 and 16 Counter using Flip-Flop

Counter plays a very important role into chip designing and verification. It is a very essential part of the VLSI Domain. Whenever we want to design or verify our design, most of the time we require slowing down frequencies. We can suppress this frequency using this counter by 2, 4, 8 or 16 times. Here circuit diagram and verilog code are given below.

Design 4-bit Linear Feedback Shift Register(LFSR) using Verilog Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. Find out VHDL Code Here.

Verilog Code for Sequence Detector "101101"

Here below verilog code for 6-Bit Sequence Detector "101101" is given. This code is implemented using FSM. FSM for this Sequence Detector is given in this image.

In this Sequence Detector, it will detect "101101" and it will give output as '1'.

VHDL Code for Bidirectional Bus

Here I have given a block diagram of Bidirectional Bus. This bus takes input from Data_in and gives output from Bi_Data when OE signal is high. In the same way when OE signal is low then it takes input from Bi_Data and gives output from Data_Out. Below I have mentioned input output into table.

Verilog Code for Johnson Counter

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find VHDL Code here.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

Verilog Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out VHDL Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

Features of Verilog Language

• Verilog is case sensitive.

• In verilog, Keywords are defined in lower case.

• In Verilog, Most of the syntax is adopted from "C" language.

• Verilog can be used to model a digital circuit at Algorithm, RTL, Gate and Switch level.

• There is no concept of package in Verilog.

• It also supports advanced simulation features like TEXTIO, PLI, and UDPs.

VHDL Programming Code Structure

VHDL stands for Very High speed integrated circuits Hardware Description Language. It was funded by the US Department of Defense in the 70’s and 80’s. It was established as IEEE standard IEEE 1076 in 1987. It was later updated on 1993, 2002 and 2008. Today VHDL is widely used across the industry for design description, simulation and synthesis purpose.

Here General Structure of VHDL Program is given below

·         Library Declaration

·         Package Declaration

·         User Defined Library Declaration*

·         User Defined Package Declaration*

·         Entity Declaration

o   Generic Declaration

o   Port Declaration

·         Architecture Declaration

·         Configuration Declaration

Setup Time and Hold Time

These two parameters are associated with Flip-Flop. Setup Time and Hold Time are two most important factors in Synchronous Design in VLSI Domain. If either of them is violated then Flip-Flop will not give proper output. 

Setup Time: - It’s a time interval before the Clock signal is triggered, where Data signal should be stable. So, that Data is easily sampled by the Flip-Flop.

Difference between Flip-Flop and Latch

Flip-Flop	Latch
Flip-Flop is Edge sensitive device.	Latch is Level sensitive device.
In Flip-Flop, output will change on rising or falling edge of clock signal.	In Latch, if Enable/Clock signal is high then output will change accordingly input.
So, we can say that Flip-Flop is a Synchronous version of Latch.	So, we can say that Latch is Asynchronous device.
Flip-Flop based design creates less timing problems.	Latch based design creates more timing problems.
In design Flip-Flop takes more area compared to Latch.	In design Latch takes less area compared to Flip-Flop.
In design Flip-Flop consumes more power compare to Latch.	In design Latch consumes less power compare to Flip-Flop.

Shift Operators in VHDL

Shift operators are playing very important role in VHDL language. It is very usefull to shift or rotate digits of binary numbers.

There are total six shifting operators in VHDL language.

•  sll

• It means Logical Shift Left.

• It shifts the elements in the array by n places to left and fill vacanted positions with "0".

• Ex

• "1000_1010" sll 3 will give "0101_0000".

• "1000_1010" sll -2 will give "0010_0010".