Setup Time and Hold Time

These two parameters are associated with Flip-Flop. Setup Time and Hold Time are two most important factors in Synchronous Design in VLSI Domain. If either of them is violated then Flip-Flop will not give proper output. 

Setup Time: - It’s a time interval before the Clock signal is triggered, where Data signal should be stable. So, that Data is easily sampled by the Flip-Flop.

Hold Time: - It’s the time interval after the Clock signal is triggered, where Data signal should be stable. So that Data should be captured by Flip-Flop. 

If Data signal will change in between Setup Time or Hold Time, then Flip-Flop will go into Metastable Stage, where output cannot be recognized as low or high logic.