VHDL stands
for Very High speed integrated circuits Hardware Description Language. It was
funded by the US Department of Defense in the 70’s and 80’s. It was
established as IEEE standard IEEE 1076 in 1987. It was later updated on 1993, 2002
and 2008. Today VHDL
is widely used across the industry for design description, simulation and
synthesis purpose.
Here
General Structure of VHDL Program is given below
·
Library
Declaration
·
Package
Declaration
·
User
Defined Library Declaration*
·
User
Defined Package Declaration*
·
Entity
Declaration
o
Generic
Declaration
o
Port
Declaration
·
Architecture
Declaration
·
Configuration
Declaration
- Library Declaration
o
In
this Library Declaration, predefined libraries are declared.
o
Library
is a collection of compiled VHDL design units.
o
Library
promotes sharing of compiled designs and hides source code from users.
o
WORK
and STD are the default libraries by the language.
o
All
the complied designs are put into WORK by default.
o
VHDL
doesn’t support nested libraries.
o
Syntax
to include library is
o Library library_name;
o
VHDL
also gives flexibilities to develop our own library. After compiling that
Library, we can declare that library into User Defined Library Declaration.
- Package Declaration
o A
package is a collection of the commonly used subprograms, data type and
constants.
o Package
saves coding and promotes code reuse.
o STANDARD
and TEXTIO are provided in the STD library which defines useful data types and
utilities.
o
We
can include package by given below syntax
o Use library_name.package_name.item_name;
o VHDL
also gives flexibilities to develop our own Packages. After compiling those
Packages, we can declare that Package into User Defined Package Declaration.
- Entity Declaration
o
It
defines interface between a given design and the environment in which it is
used.
o
It
can be used as a component in other entities after being compiled into library.
o
An
entity may have no port declaration.
o
We
can declare entity by given syntax
o Entity entity_name is
Generic DeclarationPort Declaration
begin
statements
end entity_name;
o
Generic
Declaration
o Generic provides a means of passing
parameters to a block from its environment or during component instantiation.
o Generic can be used to control the
model size, component instantiations, timing parameters, or any other user
defined parameter.
o Generic Declaration can be done by
given below syntax
o Generic generic_name
: data_type [:= initial value]
o
Port
Declaration
o Ports provide the communication
channel between a component and its environment.
o A port is a signal with a specified
data flow direction.
o There are four modes of Port
o IN:
- Input value can read but not assigned.
o OUT:
- Output value can be assigned but not read.
o INOUT:
- Bi-directional. Value can be assigned and read.
o BUFFER:
- Output with read capability.
o Port Declaration can be made by given
below syntax
o Port port_name
: port_direction data_type
- Architecture Declaration
o Architecture describes the internal
organization or operation of the design entity.
o It is used to describe the behavior,
data flow or structure of design entity.
o A single Entity can have multiple
Architectures.
o There can be no Architecture without
an Entity.
o Architecture can contain only
concurrent statements.
o VHDL Architecture can be classified into three types.
o Behavioral: - It defines a sequentially described functioning of the design.
o Structural: - It defines interconnections between previously defined components.
o Dataflow: - It is a combination of Structural and Behavioral Architecture.
o Syntax for Architecture Declaration
is given below
o Architecture architecture_name of entity_name is
declarations
begin
declarations
begin
statements
end architecture_name;
- Configuration Declaration
o A Configuration statement selects
one of several Architectures for a single Entity. Components within
Architecture can also be chosen.
o Configuration is ignored by
synthesizer.
o Unless specified, the last compiled
Architecture is used for the simulation.
o Configuration saves compile time
when some components need substitution in a large design.
o Configuration Declaration can be
made by using given syntax
o configuration configuration_name of entity_name is
for architecture_name
for instance_name:component_name
use entity
library_name.entity_name(architecture_name);
end for;
end for;
end configuration_name;
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