Features of Verilog Language

• Verilog is case sensitive.

• In verilog, Keywords are defined in lower case.

• In Verilog, Most of the syntax is adopted from "C" language.

• Verilog can be used to model a digital circuit at Algorithm, RTL, Gate and Switch level.

• There is no concept of package in Verilog.

• It also supports advanced simulation features like TEXTIO, PLI, and UDPs.