Verilog Code for Priority Resolver Type Arbiter

S.No.	Name	Direction	Width	Remark
1	Req_1	Input	1	Request for 1st user
2	Req_2	Input	1	Request for 2nd user
3	Req_3	Input	1	Request for 3rd user
4	Req_4	Input	1	Request for 4th user
5	Clk	Input	1	Clock signal
6	Rst_a	Input	1	Reset signal
7	Grant_1	Output	1	Grant for 1st user
8	Grant_2	Output	1	Grant for 2nd user
9	Grant_3	Output	1	Grant for 3rd user
10	Grant_4	Output	1	Grant for 4th user

The above design is a Priority Resolver circuit which gives priority to the requests of that user which was given grant the most earlier. In other way the user which was given grant most recently is given least priority. If the two requests have ,by chance, conflict in getting the grant, they will be issued the grant signal according to the following sequence:

req4     >          req3     >          req 2    >          req1

module priority_resolver_new (grant,req,clk,rst_a);

  //----------input output port declaration
 
   output  [3:0] grant;        //granted user
   input [3:0]   req;          //requesting user
   input   clk;          //clock
   input   rst_a;        //asynchronous reset



  //---------internal signal declaration
  reg [6:0] count [3:0];      //counter for priority resolving
  reg [3:0] temp;
  reg [3:0] tmp_grant;
  reg [2:0] j;

  assign grant = tmp_grant;
  always @(posedge clk, posedge rst_a)
  begin
    if (rst_a)
          begin
            count[0]=7'b0;
            count[1]=7'b0;
            count[2]=7'b0;
            count[3]=7'b0;
         
          end
   else if (grant[0])
        begin
                            count[0]=0;
                            count[1]=count[1]+1;
                            count[2]=count[2]+1;
                            count[3]=count[3]+1;
         end
       else if (grant[1])
        begin
                            count[0]=count[0]+1;
                            count[1]=0;
                            count[2]=count[2]+1;
                            count[3]=count[3]+1;
         end
         else if (grant[2])
        begin
                            count[0]=count[0]+1;
                            count[1]=count[1]+1;
                            count[2]=0;
                            count[3]=count[3]+1;
         end
         else if (grant[3])
        begin
                            count[0]=count[0]+1;
                            count[1]=count[1]+1;
                            count[2]=count[2]+1;
                            count[3]=0;
         end
    end
     
  always @(posedge clk,posedge rst_a)
    begin
        if (rst_a)
          begin
            tmp_grant = 4'b0;
          end
       else if (count[0]==0&&count[1]==0&&count[2]==0&&count[3]==0)//intial contion priority req[0]>req[1]>req[3]>req[4]
              begin
                if (req[0])
                  begin
                  tmp_grant[0]=1'b1;
                  tmp_grant[3:1]=3'b0;
                  end
                else if (req[1])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b1;
                  tmp_grant[2]=1'b0;
                  tmp_grant[3]=1'b0;
                  end
                else if (req[2])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b0;
                  tmp_grant[2]=1'b1;
                  tmp_grant[3]=1'b0;
                  end
                else if (req[3])
                  begin
                  tmp_grant[0]=1'b0;
                  tmp_grant[1]=1'b0;
                  tmp_grant[2]=1'b0;
                  tmp_grant[3]=1'b1;
                end
              end
            else                                                                                                                                    
                       if (!count[0]&&req[0])          //for req=0001
                         tmp_grant = 4'b0001;
                       else if (!count[1]&&req[1])    //for req=0010
                         tmp_grant = 4'b0010;
                       else if (!count[2]&&req[2])    //for req=0100
                         tmp_grant = 4'b0100;
                       else if (!count[3]&&req[3])    //for req=1000
                         tmp_grant = 4'b1000;
                       else
                          begin
                            tmp_grant = 4'b0;
                          if (req[0])
                              temp=count[0];
                          else if (req[1])
                            temp=count[1];
                           else if (req[2])
                             temp=count[2];
                           else if (req[3])
                             temp=count[3];
                           
                             for(j=3'b0;j<=3'b011;j=j+1) //for more than one req
                                begin
                                 
                                   if (req[j])
                                        if(temp<=count[j])
                                          begin
                                            tmp_grant=0;
                                          temp=count[j];
                                          tmp_grant[j]=1'b1;
                                          end
                                       else
                                          tmp_grant[j]=1'b0;
                                    else
                                         tmp_grant[j]=1'b0;  
                                end
                  end
          end
 endmodule