Verilog Code for Asynchronous Clear D-FlipFlop Using Primitive

Sr. No.	Name of the Pin	Direction	Width	Description
1	d	Input	1	Data input
2	clk	Input	1	Clock Signal
3	clear	Input	1	async clear  Signal
4	q	Output	1	Data Output

Primitive Code

primitive d_flipflop(q,clear,clk,d);
   output q;
   reg q;
   input      d,clk,clear;
   initial q=1'b1;

   table

    //clear  clk   d     q  q+
  // ------ ----- ---   --- --
      0       ?    ?   : ? : 0;      //async clear
      1      (01)  1   : ? : 1;   //rising edge
      1      (01)  0   : ? : 0;   //risinh edge
      1      (0?)  0   : ? : 0;
      1      (0?)  1   : ? : 1;
      1      (10)  ?   : ? : -;   //nochange on falling edge
      ?       ?   (??) : ? : -;  //no change on data change in stable clock
     (??)     ?    ?   : ? : -;  //no change on clear change in stable clock

   endtable
endprimitive // d_flipflop

Main Module Code

module d_ff_module(q,qb,clk,d,clear);
   output q,qb;
   input  clk;
   input  d;
   input  clear;

   d_flipflop g1(q,clear,clk,d);
   not g2(qb,q);

endmodule // d_ff_module