Verilog Code for 4x1 Multiplexer Using Primitive

Sr. No.	Name of the Pin	Direction	Width	Description
1	Ip	Input	4	Input to be muxed
2	Sel	Input	2	Select Lines
3	Op	Output	1	Muxed Output

Primitive Code

primitive mux_4x1(muxed_out,sel_1,sel_0,data1,data2,data3,data4);

   output muxed_out;
   input  sel_1,sel_0;
   input  data1,data2,data3,data4;


   table

      //sel_1 sel_0 data1 data2 data3 data4

      0 0 1 ? ? ? :1;
      0 0 0 ? ? ? :0;
      0 1 ? 1 ? ? :1;
      0 1 ? 0 ? ? :0;
      1 0 ? ? 1 ? :1;
      1 0 ? ? 0 ? :0;
      1 1 ? ? ? 1 :1;
      1 1 ? ? ? 0 :0;
      x x 0 0 0 0 :0;
      x x 1 1 1 1 :1;
      ? ? 1 1 1 1 :1;
      ? ? 0 0 0 0 :0;

   endtable
endprimitive // mux_4x1

Main Module Code

module mux4x1_module(op,sel,ip);
  output op;
  input [1:0] sel;
  input [3:0] ip;

  mux_4x1 g1(op,sel[1],sel[0],ip[0],ip[1],ip[2],ip[3]);

endmodule