Design 4-Bit Up-Down Counter using Verilog Code

This 4-bit Up Down counter has five input signals and one output signal. Rst_a is asynchronous reset signal. clk is clock signal. Load is used to load counter with predefined input value. Up_down is for counting up or counting down operation. Enable is to enable output signal. Op is four bits wide output signal that will give counted value.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Rst_a	Input	1	Reset Signal
2	clk	input	1	clock signal
3	Load	Input	1	Load the predefined input
4	Up_down	Input	1	‘1’ up counting ‘0’ down counting
5	Enable	Input	1	For output enable
6	Op	Output	4	Output

`define width 4
`define ip 0111
module up_down_counter(op,up_down,load,enable,clk,rst_a);

   output [`width-1:0] op;
   input   up_down;
   input   load;
   input   enable;
   input   clk;
   input   rst_a;

   reg [`width-1:0]  tmp_ip;

assign op=tmp_ip;
always @(posedge clk,posedge rst_a)
begin
   if(rst_a)
  tmp_ip=0;
   else
 begin
     if(load)
       tmp_ip=`ip;
     else
       begin
         if(enable)
           begin
          if (up_down)
          tmp_ip=tmp_ip+1;
   else
                 tmp_ip=tmp_ip-1;
          end
        end
     end
  end
endmodule