Verilog Code for 16x4 Memory

Sr. No.	Name of the Pin	Direction	Width	Description
1	Address	Input	4	Input address
2	Ip	input	4	Input data to memory
3	Rd_wr	Input	1	Control signal 1=read from memory 0=write in to memory
4	Clk	Input	1	Clock input
5	op	Output	4	Output read from memory

module memory_16x4(op,ip,rd_wr,clk,address);
   output reg [3:0] op;
   input [3:0]  ip;
   input [3:0] address;
   input  rd_wr,clk;
   reg [3:0]  memory[0:15];



   always @(posedge clk)
     begin
       if (rd_wr)
         op=memory[address];
       else
         begin
           memory[address]=ip;
       end
     end
endmodule // memory_16x4