Verilog Code for 4-Bit Sequential Multiplier Using Booths Algorithm

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	4	Data Input
2	b	Input	4	Data Input
3	Load	Input	1	Load Input
4	Rst_a	Input	1	Reset Input
5	Clk	Input	1	Clock Input
6	Op	Output	8	Multiplied Output

module booth_seq_multi(op,clk,rst_a,load,a,b);

   //parameter declaration-----------------------------
   parameter ip1_data_width = 4;
   parameter ip2_data_width = 4;
   parameter op_data_width  = ip1_data_width + ip2_data_width;
   parameter reg_data_width =ip1_data_width + ip2_data_width + 1;
 
   integer i;
 
   //input output declaration------------------
   output reg [op_data_width-1:0] op;
   input             clk,rst_a,load;
   input [ip1_data_width-1:0]    a;
   input [ip2_data_width-1:0]    b;
 
   //register declaration------------------------
   reg [reg_data_width-1:0]  tmp_a,tmp_s,tmp_p;
   reg [ip1_data_width-1:0]  tmp_abar,tmp_a2s,tmp_a1,tmp_b;
 
 
  always @(posedge clk)
    begin
       if(load)                  // Register the inputs
  begin
     tmp_a1=a;
     tmp_b=b;
  end
    end
 
   always @ (posedge clk,posedge rst_a)
   begin
 if(rst_a)
   op=0;
 else
   begin
    if(~load)
      begin
  tmp_abar= ~ tmp_a1;
  tmp_a2s = (tmp_abar + 1'b1);  
  tmp_a={tmp_a1,5'b00000};
  tmp_s={tmp_a2s,5'b00000};
  tmp_p={4'b0000,tmp_b,1'b0};
  
  for(i=0;i<4;i=i+1)
    begin
       case(tmp_p[1:0])

         2'b00 : tmp_p = {tmp_p[8],tmp_p[8:1]};
         2'b01 :begin tmp_p =tmp_p + tmp_a;
                      tmp_p = {tmp_p[8],tmp_p[8:1]};
                end
         2'b10 :begin tmp_p = tmp_p + tmp_s;
                      tmp_p = {tmp_p[8],tmp_p[8:1]};
                       end
         2'b11 : tmp_p = {tmp_p[8],tmp_p[8:1]};
         default: tmp_p = 9'bx;
       endcase // case (tmp_p[1:0])
    end // for (i=0;i<4;i=i+1)

           op=tmp_p[8:1];
      end // if (~load)
    end // else: !if(rst_a)
  end
endmodule // booth_seq_multi