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Thursday, 10 March 2016

A Brief Overview Of Data Type in VHDL.

VHDL is strongly typed language and it supports a variety of Data Types and Operators. Users can also define their own data types and operators in user defined packages. There are three basic classes to define data objects in VHDL language.
  • Signal : It represents interconnections that connect components and parts.
  • Variable : It is used for local storage within process.
  • Constant : It is used to declare a fixed value.
The data object can be a scalar or an array (one dimensional as well as multi dimensional).

Saturday, 27 February 2016

Get Knowledge of Operators in VHDL with Examples

VHDL has wide range of Operators, which can be grouped into following
  • Logical Operators
  • Relational Operators
  • Shift Operators.
  • Miscellaneous Operators

Wednesday, 10 February 2016

Get Knowledge of Delay Types in VHDL

In VHDL, delays are specified only in signal assignment not in variable assignment. Delays are not synthesizable. There are two types of delay in VHDL Language.
  1. Transport Delay
  2. Inertial Delay
  • Transport Delay : It is the delay model just delay the signal or change the value of the signal by the time specified in the after clause. It is the characteristic of the hardware elements that exhibits infinite frequency response. Any pulse is transmitted no matter how small it is.

Monday, 8 February 2016

Design BCD to 7-Segment Decoder using VHDL Code

Given below VHDL code will convert 4 bit BCD into equivalent seven segment number. It will accept 4 bit input and generate seven bit output. One seven segment can show zero to nine digit, so there is 4 bit input. Code is written for Common Cathode seven segment LED.So, LEDs will glow when the input is high. Find out Verilog Code here.
Common Cathode Seven Segment Display

Friday, 29 January 2016

Design Johnson Counter and Test with Test Bench using VHDL Code

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find out Verilog Code here.

Sr. No.
Name of the Pin
Direction
Width
Description
1
Clk
Input
1
Clock Signal
2
Rst
Input
1
Reset Signal
3
Op
Output
4
Output Signal