Design Johnson Counter and Test with Test Bench using VHDL Code

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find out Verilog Code here.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Op	Output	4	Output Signal

VHDL Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out Verilog Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Op	Output	4	Output Signal

Verilog and VHDL Code for Digital Clock

Given below code is Simple Digital Clock. It accepts one input as 50 MHz clock and gives three output as Hour, Minute and Second. This code converts internally 50 MHz into 1 Hz Clock Frequency. In this code first process converts frequency from 50 MHz to 1 Hz. in the second process at every clock event second value will increment but up to 59 and then again zero. Same way Minute value will also increment after second value will reach to 59, but up to 59. Hour value will increment when minute value reaches to 59 and goes up to 23 and again goes to zero. In the last integer values of ss, mm and hr are converted into standard logic vector and assign to Second, Minute and Hour respectively. If you want to display this clock on your 7 segment or LCD display then you have write another code that accepts these inputs and generates equivalent output to be displayed.

VHDL Code for Bitonic Sorter

Bitonic Sorter is one kind of Sorting Algorithm. This algorithm invented by Ken Batcher. You can find more detail about this algorithm over here.

Bitonic Sorter

VHDL Code for Generation of 1 KHz and 1 Hz Frequency from 100 MHz Frequency

Given below VHDL code will generate 1 kHz and 1 Hz frequency at the same time. This design takes 100 MHz as a input frequency. For this we need counter with different values and that will generate above frequencies. There is a simple formula to find this count value and it is given below.

Count Value = (Input Frequency) / (2 * Output Frequency).

In our case Count Value for 1 kHz is (100 * 10^6) / (2 * 1 * 10^3) = 50,000. After 50,000 count, level of msClk will change.

and for 1 Hz is (100 * 10^6) / (2 * 1) = 5,00,00,000.

Name of Pins	Direction	Data Width
sysClk	Input	1
msClk	Output	1
secClk	Output	1