We’ve seen in the last few posts mastering Clock Domain Crossing (CDC)—learning how to safely move single bits, multi-bit buses, and fleeting pulses across different clock domains without triggering metastability.
Today, we are looking at a signal that goes to almost every single flip-flop in your entire design: The Reset Signal.
In academia, the reset is just a theoretical switch that initializes your system. In the real world, releasing a reset at the wrong time will send your entire chip or FPGA into a catastrophic, unrecoverable metastable state. Let’s explore why this happens and how industry experts fix it.
Synchronous vs. Asynchronous Resets
When designing RTL, you generally have two choices for how to implement your resets:
Synchronous Resets: The flip-flop only clears its value on the active edge of the clock.
Pros: Completely immune to metastability from the reset signal itself.
Cons: If your clock is turned off (e.g., to save power), you cannot reset the chip!
Asynchronous Resets: The flip-flop clears its value the instant the reset signal is asserted, regardless of what the clock is doing.
Pros: Works perfectly even if the clocks are stopped or haven't stabilized yet.
Cons: Extremely dangerous when you release the reset.
Because modern System-on-Chips (SoCs) use aggressive clock-gating to save power, Asynchronous Resets are the industry standard. But they come with a massive hidden trap.