Data Types in Verilog Language

A Data Type is a classification of various class of Data, such as Real, Integer or Boolean. And It is important because it determines the value of that type; which operation can be done on values of that type; the real meaning of that data. Every language has its own Data Type.

In the same way, Verilog has it's own Data Types. There are mainly eight Data Types in Verilog which are listed below.

1. Value Set
2. Nets
3. Registers
4. Integers
5. Time
6. Real
7. Parameter
8. Arrays

These Data Types are explained further below.

• Value Set Data Type
• Verilog Supports four basic values for this particular Data Type
• "0" - Logic zero or false condition
• "1" - Logic one or true condition
• "X" - Unknown logic value
• "Z" - high impedance
• Values "X" and "Z" are case-insensitive.
•  Constants in verilog are made up of these four basic values.

• Net Data Type
• It represents a physical connection between structural elements.
• If no driver is connected, then its default value will be "z".
• Net declaration is defined as follows
  net_kind [msb : lsb] net1, net2,....,netN
• Wire is the mostly used net data type.
• Other net data type are "wand", "wor", "tri", "trior" etc.
• For Example
  wire sum, count, a,b;
  wire [2:0] address;

• Register Data Type
• It represents an data storage element.
• This Data Type only assigned within an always or initial statements.
• Its value is saved from one assignment to the next.
• It is used to model synchronous hardware and to apply stimulus in test bench.
• Reg kind of register is mostly used.
• It has default value of "x".
• It can be used as
  reg [msb:lsb] reg1, reg2,...,regN
• Values stored in registers are interpreted as unsigned number.
• For Example
  reg [3:0] sum;
  reg chi

• Integer Data Type
• It holds integer values.
• It can be used as general purpose variable.
• It holds a minimum of 32 bits.
• It holds only signed values.
• For Example
  integer a,b,c;

• Time Data Type
• It is used to store and manipulate time values.
• It holds at least 64 bits of time value.
• It holds only unsigned quantity and it is not supported in synthesis.
• For Example
  time chi
  chi = $time // chi = current simulation time

• Real Data Type
• It has default value of "0".
• It is declared as
  real real1, real2,...,real3;

• Parameter Data Type
• It is defined as constant with in the module.
• It can not be used as variables.
• Value of this Data Type can be changed at any instant.
• For Example
  parameter clk_period = 20;

• Array Data Type
• Verilog supports one dimensional as well as multidimensional for above most Data Type.
•  This Data Type can be used using reg, integer, time, real or wire kind of Data Types.