VHDL Code for 3x8 Decoder

A Decoder is a combinational logic circuit which converts code into a set of signals. It is exactly opposite of Encoder. It is mostly used to generate selection or enable line in a digital circuit. Find out Test Bench for 3x8 Decoder in VHDL over here.

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library ieee;
use ieee.std_logic_1164.all;

entity deco3x8_seq is
  
  port (
    ip : in  std_logic_vector(2 downto 0);   -- input
    op : out std_logic_vector(7 downto 0));  -- output

end deco3x8_seq;

architecture beh of deco3x8_seq is

begin  -- beh

deco : process (ip)
  variable temp : std_logic_vector(7 downto 0);
  begin
    case ip is
      when "000" => temp := "00000001";
      when "001" => temp := "00000010";
      when "010" => temp := "00000100";
      when "011" => temp := "00001000";
      when "100" => temp := "00010000";
      when "101" => temp := "00100000";
      when "110" => temp := "01000000";
      when "111" => temp := "10000000";
      when others => temp := "XXXXXXXX";
    end case;
    op <= temp;
 end process deco;
end beh;