- Verilog is very popular Hardware Description language. It was introduced by Gateway Design Automation in 1984. In 1989, Cadence Design Systems purchased and put into public domain in 1990. In 1993, OVI enhanced the verilog language but that was not well accepted. IEEE standardized the Verilog HDL(IEEE 1364-1995) in 1995. In 2001, extension to verilog-95 submitted to IEEE and accepted verilog IEEE std 1364-2001. The revision of the language is also done in 2002 and 2005.
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Sunday, 13 March 2016
Quick Overview To Start Coding into Verilog
Thursday, 10 March 2016
A Brief Overview Of Data Type in VHDL.
VHDL is strongly typed language and it supports a variety of Data Types and Operators. Users can also define their own data types and operators in user defined packages. There are three basic classes to define data objects in VHDL language.
- Signal : It represents interconnections that connect components and parts.
- Variable : It is used for local storage within process.
- Constant : It is used to declare a fixed value.
The data object can be a scalar or an array (one dimensional as well as multi dimensional).
Saturday, 27 February 2016
Get Knowledge of Operators in VHDL with Examples
VHDL has wide range of Operators, which can be grouped into following
- Logical Operators
- Relational Operators
- Shift Operators.
- Miscellaneous Operators
Wednesday, 10 February 2016
Get Knowledge of Delay Types in VHDL
In VHDL, delays are specified only in signal assignment not in variable assignment. Delays are not synthesizable. There are two types of delay in VHDL Language.
- Transport Delay
- Inertial Delay
- Transport Delay : It is the delay model just delay the signal or change the value of the signal by the time specified in the after clause. It is the characteristic of the hardware elements that exhibits infinite frequency response. Any pulse is transmitted no matter how small it is.
Monday, 8 February 2016
Design BCD to 7-Segment Decoder using VHDL Code
Given below VHDL code will convert 4 bit BCD into equivalent seven segment number. It will accept 4 bit input and generate seven bit output. One seven segment can show zero to nine digit, so there is 4 bit input. Code is written for Common Cathode seven segment LED.So, LEDs will glow when the input is high. Find out Verilog Code here.
Common Cathode Seven Segment Display |
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