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Wednesday 23 July 2014

Implement Divide by 2, 4, 8 and 16 Counter using Flip-Flop

Counter plays a very important role into chip designing and verification. It is a very essential part of the VLSI Domain. Whenever we want to design or verify our design, most of the time we require slowing down frequencies. We can suppress this frequency using this counter by 2, 4, 8 or 16 times. Here circuit diagram and verilog code are given below.


Monday 21 July 2014

Design 4-bit Linear Feedback Shift Register(LFSR) using Verilog Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. Find out VHDL Code Here.

Saturday 12 July 2014

Verilog Code for Sequence Detector "101101"

Here below verilog code for 6-Bit Sequence Detector "101101" is given. This code is implemented using FSM. FSM for this Sequence Detector is given in this image.

In this Sequence Detector, it will detect "101101" and it will give output as '1'.









Thursday 10 July 2014

VHDL Code for Bidirectional Bus

Here I have given a block diagram of Bidirectional Bus. This bus takes input from Data_in and gives output from Bi_Data when OE signal is high. In the same way when OE signal is low then it takes input from Bi_Data and gives output from Data_Out. Below I have mentioned input output into table.








Friday 4 July 2014

Verilog Code for Johnson Counter

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find VHDL Code here.

Sr. No.
Name of the Pin
Direction
Width
Description
1
Clk
Input
1
Clock Signal
2
Rst
Input
1
Reset Signal
3
Out
Output
4
Output Signal