Get Familiar with System Task in Verilog

There are special Tasks and Function in Verilog language which are used to generate input and output during simulation process. These special Tasks and Functions are always starts with $ sign, followed by Task/Function specifier. Synthesis tools ignore these system tasks and functions.

These System Tasks are classified as below

• Display Task
• $display, $write, $monitor, $strobe
• File I/O Task
• $fopen, $fclose, $fdisplay, $fstrobe, $fmonitor
• Timescale Task
• $time, $stime, $realtime
• Simulation Control Task
• $reset, $finish, $stop
  

Easy UVM (Universal Verification Methodology) Tutorial

UVM stands for Universal Verification Methodology. It is standard methodology to verify Integrated Circuits. UVM is derived from OVM, Open Verification Methodology. UVM is developed by Accellera with the support of Aldec, Cadence, Mentor Graphics and Synopsys. UVM is based on System Verilog language. With the help of UVM, engineers are able to create an efficient verification environment. It is portable from one project to another. Due to portability, engineers can reuse testbench from previous projects and modify different components as per their need. UVM easy tutorial is shown below. It is available on YouTube. It is developed by John Aynsley from Doulos. There are twenty videos. After watching this tutorial, overall picture of UVM will be cleared. 

Verilog Code for (7,4) Systematic Hamming Encoder

Hamming code is useful in Error Correction in Linear Block Code. This code will encode four bits of data and generate seven bits of code by adding three bits as parity bits. It was introduced by Richard W. Hamming. This algorithm can detect one and two bit error and can correct one bit error. Given below code will generate (7,4) Systematic Hamming Encoder. This encoder will use Least Significant 4 bits as data inputs and Most 3 significant bits as a parity bits.

Get VHDL Code.

Design a Constant Divider using VHDL Coding.

Constant Divider circuit accepts an input of 8 bit wide and divides it by constant value 53. The divider circuit will generate two output values as remainder and quotient. As we know that the division operator is not synthesizable, so division is done by repetitive subtraction method. As an example of input is 108, the remainder is 2 and quotient is 2 while if input is 20, remainder is 20 and quotient is 0. In this design Inp is input with 8 bit long, Remi and Quo are two output signals with 6-bit and 3-bit long respectively. Here bit lengths of Remi and Quo are decided as per getting maximum value. Divider is constant which is 8 bit long and value is "00110101". Binary value of 53 is "00110101".

Design 4-bit Linear Feedback Shift Register (LFSR) using VHDL Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. It is used for State Encoding. It is also used to generate random numbers. Find out Verilog code here.