Design Traffic Light Controller using Verilog FSM Coding and Verify with Test Bench

Given below code is design code for Traffic Light Controller using Finite State Machine(FSM). In this clk and rst_a are two input signal and n_lights, s_lights, e_lights and w_lights are 3 bit output signal. In output signal, "001" represents Green light, "010" represents Yellow light and "100" represents Red light. On the reset signal, design will enter into north state and start giving output after reset will go low. Design will turn on Green light for eight clock cycles and Yellow light for four clock cycles. Design will start with north, then goes into south, then east and finally into west and by this it will keep going.

Sr. No.	Name of the Pin	Direction	Width	Description
1	n_lights	Output	3	North Lights  (001 = Green, 010 = Yellow, 100 = Red)
2	s_lights	Output	3	South Lights (001 = Green, 010 = Yellow, 100 = Red)
3	e_lights	Output	3	Eight Lights  (001 = Green, 010 = Yellow, 100 = Red)
4	w_lights	Output	3	West Lights (001 = Green,  010 = Yellow, 100 = Red)
5	clk	Input	1	Clock Signal
6	Rst_a	Input	1	Reset Signal

Verilog Code for Asynchronous Clear D-FlipFlop Using Primitive

Sr. No.	Name of the Pin	Direction	Width	Description
1	d	Input	1	Data input
2	clk	Input	1	Clock Signal
3	clear	Input	1	async clear  Signal
4	q	Output	1	Data Output

Verilog Code for 4x1 Multiplexer Using Primitive

Sr. No.	Name of the Pin	Direction	Width	Description
1	Ip	Input	4	Input to be muxed
2	Sel	Input	2	Select Lines
3	Op	Output	1	Muxed Output

Verilog Code for Priority Resolver Type Arbiter

S.No.	Name	Direction	Width	Remark
1	Req_1	Input	1	Request for 1st user
2	Req_2	Input	1	Request for 2nd user
3	Req_3	Input	1	Request for 3rd user
4	Req_4	Input	1	Request for 4th user
5	Clk	Input	1	Clock signal
6	Rst_a	Input	1	Reset signal
7	Grant_1	Output	1	Grant for 1st user
8	Grant_2	Output	1	Grant for 2nd user
9	Grant_3	Output	1	Grant for 3rd user
10	Grant_4	Output	1	Grant for 4th user

The above design is a Priority Resolver circuit which gives priority to the requests of that user which was given grant the most earlier. In other way the user which was given grant most recently is given least priority. If the two requests have ,by chance, conflict in getting the grant, they will be issued the grant signal according to the following sequence:

req4     >          req3     >          req 2    >          req1

Design 4-Bit Up-Down Counter using Verilog Code

This 4-bit Up Down counter has five input signals and one output signal. Rst_a is asynchronous reset signal. clk is clock signal. Load is used to load counter with predefined input value. Up_down is for counting up or counting down operation. Enable is to enable output signal. Op is four bits wide output signal that will give counted value.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Rst_a	Input	1	Reset Signal
2	clk	input	1	clock signal
3	Load	Input	1	Load the predefined input
4	Up_down	Input	1	‘1’ up counting ‘0’ down counting
5	Enable	Input	1	For output enable
6	Op	Output	4	Output