VHDL Code for Synchronous FIFO

Sr. No.	Name of the Pin	Direction	Width	Description
1	Rst_a	Input	1	Reset Input
2	Clk	Input	1	Clock Input
3	we	Input	1	when high write into fifo and when low read from memory
5	Data_in	Input	8	Data Input
6	Data_out	Output	8	Data output
7	Full	Output	1	Fifo status 1 if fifo is full
8	Empty	Output	1	Fifo status 1 if fifo is empty

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity fifo is
  
  generic (
    addr_width : integer := 4;          -- address width
    data_width : integer := 8);         -- data_width

  port (
    data_in  : in  std_logic_vector(7 downto 0);  -- data
    data_out : out std_logic_vector(7 downto 0);  -- data_out
    clk      : in  std_logic;           -- clock signal
    rst      : in  std_logic;           -- reset signal
    we       : in  std_logic;           --write enable signal
    full     : out  std_logic;           -- full signal
    empty    : out std_logic);          -- empty signal

end fifo;

architecture beh of fifo is
constant depth : integer := 2**addr_width;  -- depth of ram

signal rd_point : std_logic_vector(addr_width-1 downto 0) := "0000";  -- read pointer

signal wr_point : std_logic_vector(addr_width-1 downto 0) := "0000";  -- write pointer

signal status : std_logic_vector(addr_width-1 downto 0) := "0000";  -- status pointer

signal ram_out : std_logic_vector(data_width-1 downto 0);  -- data out from ram

signal full_s,empty_s : std_logic;


component dual_port_ram 
generic (
    addr_width : integer := 4;          -- address width
    data_width : integer := 8);         -- data_width

 port (
    address1  : in  std_logic_vector(addr_width-1 downto 0);  -- address for port1
    data1     : in  std_logic_vector(data_width-1 downto 0);  -- data for port1
    we1       : in  std_logic;                     -- write enable for port1
    address2  : in  std_logic_vector(addr_width-1 downto 0);  -- address for port2
    data2     : in  std_logic_vector(data_width-1 downto 0);  -- data for port2
    we2       : in  std_logic;                     -- write enable for port 2
    data_out1 : out std_logic_vector(data_width-1 downto 0);  -- data_out for port 1
    data_out2 : out std_logic_vector(data_width-1 downto 0);  -- data out for port 2
    clk       : in  std_logic                     -- clock signal
   );                    -- reset signal

end component;
  
begin  -- beh


  full_s <= '1' when (status=(depth-1)) else '0';
  empty_s <= '1' when (status="0000") else '0';
  full<=full_s;
  empty<=empty_s;

  read_pointer: process (clk,rst)
  begin  -- process read_pointer
    if rst='1' then
      rd_point<="0000";
    elsif rising_edge(clk) then
      if we='0' then
        rd_point<=rd_point+'1';
      end if;
    end if;
  end process read_pointer;


  write_pointer: process (clk,rst)
  begin  -- process write_pointer
    if rst='1' then
      wr_point<="0000";
    elsif rising_edge(clk) then
      if we='1' then
        wr_point<=wr_point+'1';
      end if;
    end if;
  end process write_pointer;


  status_count: process (clk,rst)
  begin  -- process status
    if rst='1' then
      status<="0000";
    elsif rising_edge(clk) then
      if we='1' and status /= "1111" then
        status<=status+'1';
      elsif we='0' and status /= "0000" then
        status<=status-'1';        
      end if;
    end if;
  end process status_count;

assertions : process (we,full_s,empty_s)
begin
    if (full_s='1') then
       assert we='0' report "ram is full & you are overwritting to ram" severity error;
  elsif (empty_s='1') then
       assert we='1' report "ram is empty & you are reading the previos data from ram" severity error; 
  end if;
end process assertions;



  u1: dual_port_ram   
  generic map (
    addr_width => 4,          -- address width
    data_width => 8)         -- data_width

  port map (
      address1  => wr_point,
      data1     => data_in,
      we1       => we,
      clk       => clk,
      address2  => rd_point,
      data2     => data_in,
      data_out2 => data_out,
      data_out1 => open,
      we2       => we
      );
  

end beh;

VHDL Code for 16x9 True Dual Port Memory

Name of the Pin	Direction	Width	Description
address1	Input	4	Input address1 i.e. address bus1
address2	Input	4	Input address2 i.e. address bus2
we1	Input	1	If 0 write in to memory & if 1 read from memory
we2	Input	1	If 0 write in to memory & if 1 read from memory
data1	Input	9	input data1
data2	Input	9	input data2
data_out1	output	9	output data1
data_out2	output	9	output data2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity dual_port_ram is

  port (
    clk            : in std_logic;      -- clk is the clock input.

    ce_l_1, ce_l_2 : in std_logic;  -- ce_l_1, ce_l_2 is the chip enable of port 1 and port 2.

    oe_l_1, oe_l_2 : in std_logic;  -- oe_l_1, oe_l_2 is active low output enable of port 1 and port 2.

    r_w_1, r_w_2   : in std_logic;  -- r_w_1, r_w_2 is read/write signal of port 1 and port 2.

    data_1, data_2 : inout std_logic_vector(8 downto 0);  -- data_1 and data_2 is the data input & output from the memory.

    addr1          : in std_logic_vector(3 downto 0);  -- addr1 is the address for port 1
    addr2          : in std_logic_vector(3 downto 0));  -- addr_2 is the address input for port 2.

end dual_port_ram;

architecture dp_ram of dual_port_ram is

  signal cntrl_1_p1, cntrl_2_p1, cntrl_1_p2, cntrl_2_p2 : std_logic;  -- cntrl_1_p1, cntrl_2_p1, cntrl_1_p2, cntrl_2_p2 are used to generate control signals for reading or writing into memory.

  type mem is array (15 downto 0) of std_logic_vector(8 downto 0);  -- mem is used to define memory.

  shared variable memory : mem;         -- memory is used to define memory.

begin  -- dp_ram

  cntrl_1_p1 <= not((not ce_l_1) and (not r_w_1)); -- control signal for read/write operation for port 1.

  cntrl_2_p1 <= not((not ce_l_1) and (not oe_l_1)); -- control signal for output enable for port 1.

  cntrl_1_p2 <= not((not ce_l_2) and (not r_w_2)); -- control signal for read/write operation for port 2.

  cntrl_2_p2 <= not((not ce_l_2) and (not oe_l_2)); -- control signal for output enable for port 2.

  ----------------------------------------------
  -- purpose: It is used to access port 1.
  -- type   : sequential
  -- inputs : clk, ce_l_1, oe_l_1, r_w_1, data_1
  -- outputs: data_1
  ----------------------------------------------
  port1: process (clk)
  begin  -- process port1
    if clk'event and clk = '1' then  -- rising clock edge
      if cntrl_1_p1 = '0' and cntrl_2_p1 = '1' then  -- Write Operation.
        memory(conv_integer(addr1)) := data_1;
      elsif cntrl_1_p1 = '1' and cntrl_2_p1 = '0' then  -- Read Operation.
        data_1 <= memory(conv_integer(addr1));
      else
        data_1 <= "ZZZZZZZZZ";
      end if;
    end if;
  end process port1;


  -------------------------------------------------------
  -- purpose: It is used to accesss port 2.
  -- type   : sequential
  -- inputs : clk, cs_l_2, oe_l_2, addr_2, data_2, r_w_2
  -- outputs: data_2
  -------------------------------------------------------
  port2: process (clk)
  begin  -- process port2
    if clk'event and clk = '1' then  -- rising clock edge
      if cntrl_1_p2 = '0' and cntrl_2_p2 = '1' then  -- Write Operation.
        memory(conv_integer(addr2)) := data_2;
      elsif cntrl_1_p2 = '1' and cntrl_2_p2 = '0' then  -- Read Operation.
        data_2 <= memory(conv_integer(addr2));
      else
        data_2 <= "ZZZZZZZZZ";
      end if;
    end if;
  end process port2;

end dp_ram

VHDL Code for 16x9 Memory

Sr. No.	Name of the Pin	Direction	Width	Description
1	addr	Input	4	Input address i.e. address bus
2	oe	input	1	output enable
3	wr_l	Input	1	If 0 write in to memory & if 1 read from memory
4	data	Input/Output	9	Output read/write from/to memory i.e. bidirectional data bus MSB is parity bit

Memory Code

library IEEE;
use IEEE.std_logic_1164.all;

entity memory is
 port (data : inout std_logic_vector (8 downto 0);  -- databus
         
   addr : in std_logic_vector (3 downto 0);     -- address bus
         
  oe, wr_l, clk : in std_logic);             -- control signals

end entity;

architecture arch  of memory is

  ----------------------------------------
  -- Instantiation of D flipflop component
  ----------------------------------------
  component d_ff is
    port (d_in , en , clk : in std_logic;
          q : out std_logic);
  end component;

  -------------------------------------
  -- Instantiation of Decoder component
  -------------------------------------
  component decoder_4x16 is

    port (
      i : in  std_logic_vector (3 downto 0);   -- input ports
      o : out std_logic_vector (15 downto 0));  -- output ports

  end component;

  -----------------------------------
  -- Instantiation of Tristate buffer
  -----------------------------------
  component tri_state is

    port (
      en    : in  std_logic;
      d_in  : in  std_logic_vector (8 downto 0);
      d_out : out std_logic_vector (8 downto 0));

  end component;
-------------------------------
-- function to calculate parity
-------------------------------
   function parity_gen_func (par : in std_logic_vector (7 downto 0)) return std_logic is
  begin

  return par(0)xor par(1)xor par(2)xor par(3)xor par(4)xor par(5)xor par(6)xor par(7);

  end parity_gen_func;

 
  type temp is array ( 15 downto 0) of std_logic_vector (8 downto 0);

  signal row : std_logic_vector (15 downto 0);  -- temporary row address container

  signal d_ff_out : temp;               -- temporary data

  signal en_tri_state : std_logic_vector (15 downto 0);  --enable signal for
                                                         --tristate buffer

begin  -- arch

  --------------------------
  -- Memory address decoding
  --------------------------
  dec: decoder_4x16 port map (i => addr,
                             o => row);

  -----------------------------------------------
  --Selecting flipflop for row and column address
  -----------------------------------------------
 
  generate_dff_coloumn:  for i in 7 downto 0 generate
    generate_dff_row: For j in 15 downto 0 generate
    dff: d_ff port map (
      d_in => data(i),
      en => row(j),
      clk => clk,
      q => d_ff_out(j)(i));
  end generate generate_dff_row;
end generate generate_dff_coloumn;

  generate_row_8 :  for i in 15 downto 0 generate
    assert data(8)=parity_gen_func(data(7 downto 0)) report "parity error" severity error;
    dff1 : d_ff port map (
                              d_in => data(8),
                              en => row(i),
                              clk => clk,
                              q => d_ff_out(i)(8));
      end generate generate_row_8;


    --------------------------------------------------------
    --Tristate buffer for input/output operation for data bus
    --------------------------------------------------------
    generate_tri_state: for i in 15 downto 0 generate
      tri_state_buffer: tri_state port map (
        en => en_tri_state(i),
        d_in => d_ff_out(i),
        d_out => data);
    end generate generate_tri_state;

    -----------------------------------
    --Enable signal for tristate buffer
    -----------------------------------
    process(row,wr_l,oe)
    begin
      for i in 15 downto 0 loop
        en_tri_state(i) <= ((oe and wr_l) and (row(i)));
    end loop;
 
    end process;
 
end arch ;

D_ff Code

library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff is
port (d_in , en , clk : in std_logic;
 q : out std_logic);
end entity;

architecture arch of d_ff is
begin
  process(clk,en,d_in)
    begin
    if (en='1') then
      if (clk'event and clk='1') then 
        q <= d_in;
      end if;
    end if;
  end process;
end arch;

Decoder_4x16 Code

library ieee;
use ieee.std_logic_1164.all;

entity decoder_4x16 is
  
  port (
    i : in  std_logic_vector (3 downto 0);   -- input ports
    o : out std_logic_vector (15 downto 0));  -- output ports

end decoder_4x16;

architecture arch of decoder_4x16 is

begin  -- deoder_concr_arch

  with i select
    o <=
    "0000000000000001" when "0000",
    "0000000000000010" when "0001",
    "0000000000000100" when "0010",
    "0000000000001000" when "0011",
    "0000000000010000" when "0100",
    "0000000000100000" when "0101",
    "0000000001000000" when "0110",
    "0000000010000000" when "0111",
    "0000000100000000" when "1000",
    "0000001000000000" when "1001",
    "0000010000000000" when "1010",
    "0000100000000000" when "1011",
    "0001000000000000" when "1100",
    "0010000000000000" when "1101",
    "0100000000000000" when "1110",
    "1000000000000000" when "1111",
    "XXXXXXXXXXXXXXXX" when others;

end arch;

Tri-state Code

library IEEE;
use IEEE.std_logic_1164.all;

entity tri_state is
  
  port (
    en    : in  std_logic;
    d_in  : in  std_logic_vector (8 downto 0);
    d_out : out std_logic_vector (8 downto 0));

end tri_state;

architecture arch of tri_state is

begin  -- arch

    with en select
    d_out <=
    d_in when '1',
    "ZZZZZZZZZ" when '0',
    "XXXXXXXXX" when others;

end arch;

Test Bench for 8-bit Barrel Shifter in VHDL

Find out Design Code Here.

library ieee;
use ieee.std_logic_1164.all;

entity barrel_shifter_tst is

end barrel_shifter_tst;


architecture beh of barrel_shifter_tst is

    component barrel_shifter

    port (
    d_in        : in  std_logic_vector(7 downto 0);   -- input vector
    d_out       : out std_logic_vector(7 downto 0);   -- shifted output
    shift_lt_rt : in  std_logic;                      -- 0=>left_operation 1=>right_operation
    shift_by    : in  std_logic_vector(2 downto 0);   -- 000=> parallel load other=>shift amount
    clk         : in  std_logic;                      -- clock signal
    rst_a       : in  std_logic);                     -- reset signal

 
  end component;
 
signal rst_a_s : std_logic;
signal shift_lt_rt_s: std_logic;
signal shift_by_s : std_logic_vector(2 downto 0);
signal d_out_s,d_in_s : std_logic_vector(7 downto 0);
signal clk_s : std_logic := '1';          -- clk signal

begin  -- arch

  u1 : barrel_shifter port map (
  rst_a      => rst_a_s,
  clk        => clk_s,
  shift_lt_rt   => shift_lt_rt_s,
  d_in       => d_in_s,
  shift_by   => shift_by_s,
  d_out     => d_out_s);


  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 50 ns;

   clk_s <= '0';
    wait for 50 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "001";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "010";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "001";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "010";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "101";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "111";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "011";
    d_in_s <= "11001101";
    wait for 100 ns;
  end process tst;

end beh;