VHDL Code for 8-bit Barrel Shifter

Sr. No.	Name of the Pin	Direction	Width	Description
1	d_in	Input	8	data input
2	Shift_by	Input	3	shift amount
3	Rst_a	Input	1	Reset signal
4	Clk	Input	1	Clock signal
5	Shift_lt_rt	Input	1	‘0’=shift left ‘1’=shift right
6	P_load	Input	1	‘1’=receive input data ‘0’=discard input data
7	D_out	Output	8	Parallel data output

Barrel shifter takes parallel data input and give shifted output either in left or right direction by a specific shift amount. When shift_by input is “000” it will place input data at the output without shifting. For specifying shifting direction shift_lt_rt pin is used. When it is ‘0’ the block will perform left shift operation and when it is ‘1’, it will perform right operation. Find out Test Bench here.

Test Bench for Parity Generator in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity parity_generator_tst is

end parity_generator_tst;

architecture beh of parity_generator_tst is

component parity_generator
  port(clk,d_in, rst_a,valid_in : in std_logic;
       valid_out,parity_out: out std_logic;
        data_o : out std_logic_vector(7 downto 0));
end component;

signal clk_s,rst_a_s,valid_in_s,d_in_s,parity_out_s,valid_out_s : std_logic;
signal data_o_s : std_logic_vector(7 downto 0);

begin  -- beh

  u1 : parity_generator port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    valid_in  => valid_in_s,
    d_in    => d_in_s,
    valid_out => valid_out_s,
    parity_out => parity_out_s,
    data_o     => data_o_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 50 ns;

    clk_s <= '0';
    wait for 50 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '0';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '0';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '1';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

  end process tst;

end beh;

VHDL Code for Parity Generator using Function

When valid_in is ‘1’ it will accept serial input and that serial input goes for parallel output. After receiving eight bit of serial input this block converts the serial input to parallel output. Valid_out signal goes ‘1’ after receiving eight bytes of serial data & gives parallel data on the data_o. After valid_out goes high parity_out signal gives parity of the input data. Valid_out signal goes high on each eighth clock cycle & remain high for one cycle.

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity parity_generator is 

  port( clk       :in std_logic;    --clock signal
        d_in      :in std_logic;    --serial data input
        valid_in  :in std_logic;    --valid input signal
        rst_a     :in  std_logic;   --reset signal
        valid_out :out std_logic;   --valid output signal
        parity_out:out std_logic;   --parity check signal
        data_o        :out std_logic_vector(7 downto 0)); --parallel data output
       
end parity_generator; 


architecture archi of parity_generator is

--fuction to check parity of output data
function parity_chk (constant i : std_logic_vector(7 downto 0)) 
    return std_logic is 
    begin
    return (i(0) xor i(1) xor i(2) xor i(3) xor i(4) xor i(5) xor i(6) xor i(7));
end parity_chk;

 subtype cnt8 is integer range 0 to 8; 

 
    --signal tmp: std_logic_vector(7 downto 0) := "00000000";
    --signal cnt : cnt8 := 0; -- counter to count 8 serial input data.
  begin 
process (clk,rst_a)
  variable tmp: std_logic_vector(7 downto 0);
  variable cnt: cnt8 := 0;
  begin  
    if (rst_a = '1') then
      data_o<="00000000";
      valid_out<='0';
      parity_out<='-';
    elsif (clk'event and clk='1') then
      if(valid_in='1') then
        tmp:=tmp(6 downto 0)& d_in;
        cnt:=cnt+1;
      if(cnt = 8) then
        valid_out<='1';
        data_o<=tmp;
        parity_out <= parity_chk(tmp);
        cnt:=0;
      else 
        valid_out <= '0';
        parity_out <= '-';
        data_o<="XXXXXXXX";  
      end if;
    end if;
  end if;
end process;
end archi; 

Test Bench for 4-bit Up-Down Counter with Pre-Load in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity up_counter_sync_preload_tst is

end up_counter_sync_preload_tst;

architecture beh of up_counter_sync_preload_tst is

component up_counter_sync_preload
  port(clk, rst_a,load : in std_logic;
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0));
end component;

signal clk_s,rst_a_s,load_s : std_logic;
signal ip_s,q_s : std_logic_vector(3 downto 0);

begin  -- beh

  u1 : up_counter_sync_preload port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    load  => load_s,
    ip    => ip_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;

    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '1';
    ip_s <= "1101";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
  end process tst;

end beh;

VHDL Code for 4-bit Up-Down Counter with Pre-Load

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity up_counter_sync_preload is
  
  port(clk, rst_a,load : in std_logic; 
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0)); 

end up_counter_sync_preload; 

architecture archi of up_counter_sync_preload is 

   begin  
    process (clk, rst_a)
      variable tmp,cnt : std_logic_vector(3 downto 0):="0000";
      begin 
        if (rst_a='1') then 
          tmp := "0000"; 
       elsif (clk'event and clk='1') then
          cnt:=tmp; 
          if (load='1') then
          tmp := ip;
           else 
          tmp := tmp + '1';
          end if;
          assert (tmp-cnt="0001") report "count differ by 1 violate" severity warning;
      end if;
          q<=tmp;
    end process;
    

end archi;