Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
d
|
Input
|
1
|
Data input
|
2
|
clk
|
Input
|
1
|
Clock Signal
|
3
|
clear
|
Input
|
1
|
async clear Signal
|
4
|
q
|
Output
|
1
|
Data Output
|
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Showing posts with label Verilog Design Units. Show all posts
Showing posts with label Verilog Design Units. Show all posts
Thursday 7 November 2013
Verilog Code for Asynchronous Clear D-FlipFlop Using Primitive
Verilog Code for 4x1 Multiplexer Using Primitive
Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
Ip
|
Input
|
4
|
Input to be muxed
|
2
|
Sel
|
Input
|
2
|
Select Lines
|
3
|
Op
|
Output
|
1
|
Muxed Output
|
Verilog Code for Priority Resolver Type Arbiter
S.No.
|
Name
|
Direction
|
Width
|
Remark
|
1
|
Req_1
|
Input
|
1
|
Request for 1st user
|
2
|
Req_2
|
Input
|
1
|
Request for 2nd user
|
3
|
Req_3
|
Input
|
1
|
Request for 3rd user
|
4
|
Req_4
|
Input
|
1
|
Request for 4th user
|
5
|
Clk
|
Input
|
1
|
Clock signal
|
6
|
Rst_a
|
Input
|
1
|
Reset signal
|
7
|
Grant_1
|
Output
|
1
|
Grant for 1st user
|
8
|
Grant_2
|
Output
|
1
|
Grant for 2nd user
|
9
|
Grant_3
|
Output
|
1
|
Grant for 3rd user
|
10
|
Grant_4
|
Output
|
1
|
Grant for 4th user
|
The above design is a Priority Resolver circuit which gives priority to the requests of that user which was given grant the most earlier. In other way the user which was given grant most recently is given least priority. If the two requests have ,by chance, conflict in getting the grant, they will be issued the grant signal according to the following sequence:
req4 > req3 > req 2 > req1
Tuesday 5 November 2013
Design 4-Bit Up-Down Counter using Verilog Code
This 4-bit Up Down counter has five input signals and one output signal. Rst_a is asynchronous reset signal. clk is clock signal. Load is used to load counter with predefined input value. Up_down is for counting up or counting down operation. Enable is to enable output signal. Op is four bits wide output signal that will give counted value.
Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
Rst_a
|
Input
|
1
|
Reset Signal
|
2
|
clk
|
input
|
1
|
clock signal
|
3
|
Load
|
Input
|
1
|
Load the predefined input
|
4
|
Up_down
|
Input
|
1
|
‘1’ up counting
‘0’ down counting |
5
|
Enable
|
Input
|
1
|
For output enable
|
6
|
Op
|
Output
|
4
|
Output
|
Verilog Code for Synchronous FIFO
Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
Rst_a
|
Input
|
1
|
Reset Input
|
2
|
Clk
|
Input
|
1
|
Clock Input
|
3
|
wr_en
|
Input
|
1
|
when high write into fifo
|
4
|
rd_en
|
input
|
1
|
when high read from memory
|
5
|
Data_in
|
Input
|
4
|
Data Input
|
6
|
Data_out
|
Output
|
4
|
Data output
|
7
|
Full
|
Output
|
1
|
Fifo status
1 if fifo is full
|
8
|
Empty
|
Output
|
1
|
Fifo status
1 if fifo is empty
|
module sync_fifo(data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en); //---------------parametre declaration parameter data_width = 4; parameter address_width = 4; parameter ram_depth =16; //--------------input output port declaration output [data_width-1:0] data_out; output full; output empty; input [data_width-1:0] data_in; input clk; input rst_a; input wr_en; input rd_en; //--------------internal register declaration reg [address_width-1:0] wr_pointer; reg [address_width-1:0] rd_pointer; reg [address_width :0] status_count; reg [data_width-1:0] data_out ; wire [data_width-1:0] data_ram ; //--------------wr_pointer pointing to write address always @ (posedge clk,posedge rst_a) begin if(rst_a) wr_pointer = 0; else if(wr_en) wr_pointer = wr_pointer+1; end //-------------rd_pointer points to read address always @ (posedge clk,posedge rst_a) begin if(rst_a) rd_pointer = 0; else if(rd_en) rd_pointer = rd_pointer+1; end //-------------read from FIFO always @ (posedge clk,posedge rst_a) begin if(rst_a) data_out=0; else if(rd_en) data_out=data_ram; end //--------------Status pointer for full and empty checking always @ (posedge clk,posedge rst_a) begin if(rst_a) status_count = 0; else if(wr_en && !rd_en && (status_count != ram_depth)) status_count = status_count + 1; else if(rd_en && !wr_en && (status_count != 0)) status_count = status_count - 1; end // always @ (posedge clk,posedge rst_a) assign full = (status_count == (ram_depth)); assign empty = (status_count == 0); memory_16x4 #(data_width,address_width,ram_depth) u1
(.address_1(wr_pointer),.address_2(rd_pointer),.data_1(data_in),.data_2(data_ram),.wr_en1(wr_en),.rd_en2(rd_en),.clk(clk)); endmodule // sync_fifo
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