Design 8 bit Ripple Carry Adder using VHDL Coding and Verify using Test Bench

Given below code will generate 8 bit output as sum and 1 bit carry as cout.  it also takes two 8 bit inputs as a and b, and one input carry as cin. This code is implemented in VHDL by structural style. Predefined full adder code is mapped into this ripple carry adder. Full Adder code can be found here. Carry is generated by adding each bit of two inputs and propagated to next bit of inputs. If carry is generated by adding seventh bits and previous carry, then cout bit goes high.

VHDL design code is given below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity rc_adder is
port ( a : in std_logic_vector(7 downto 0);
 b : in std_logic_vector(7 downto 0);
 cin : in std_logic;
 sum : out std_logic_vector(7 downto 0);
 cout : out std_logic);
end rc_adder;

architecture structural of rc_adder is

component full_adder_con is
  port (
    a, b, c : in  std_logic;            -- inputs
    sum, ca : out std_logic);           -- sum & carry
end component;
signal carry : std_logic_vector(6 downto 0);

begin

U1 : full_adder_con port map (a(0),b(0),cin,sum(0),carry(0));
U2 : for i in 1 to 6 generate
U3 : full_adder_con port map (a(i),b(i),carry(i-1),sum(i),carry(i));
end generate;
U4 : full_adder_con port map (a(7),b(7),carry(6),sum(7),cout);

end structural;

Above code is synthesized by Xilinx Vivado and RTL view of Ripple Carry Adder is given below.

RTL view of Ripple Carry Adder

Test Bench code for above Ripple Carry Adder is given below.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity rc_adder_tst is

end rc_adder_tst;

architecture beh of rc_adder_tst is
component rc_adder is
port ( a : in std_logic_vector(7 downto 0);
 b : in std_logic_vector(7 downto 0);
 cin : in std_logic;
 sum : out std_logic_vector(7 downto 0);
 cout : out std_logic);
end component;
signal a_s,b_s,sum_s : std_logic_vector (7 downto 0);
signal cin_s,cout_s : std_logic;
begin

DUT : rc_adder port map (a_s,b_s,cin_s,sum_s,cout_s);
process
 begin
  a_s <= "10101010";
  b_s <= "01010101";
  cin_s <= '0';
  wait for 10 ns;
  
  a_s <= "11001100";
  b_s <= "11110000";
  cin_s <= '1';
  wait for 10 ns;
  
  a_s <= "11010111";
  b_s <= "01011010";
  cin_s <= '0';
  wait for 10 ns;
  
  a_s <= "10110011";
  b_s <= "11111111";
  cin_s <= '1';
  wait for 10 ns;
 end process;
 
end beh;

Above Test Bench is simulated in Xilinx Vivado and waveform is shown below.

Waveform of Ripple Carry Adder