Design 8 bit Ripple Carry Adder using VHDL Coding and Verify using Test Bench

Given below code will generate 8 bit output as sum and 1 bit carry as cout.  it also takes two 8 bit inputs as a and b, and one input carry as cin. This code is implemented in VHDL by structural style. Predefined full adder code is mapped into this ripple carry adder. Full Adder code can be found here. Carry is generated by adding each bit of two inputs and propagated to next bit of inputs. If carry is generated by adding seventh bits and previous carry, then cout bit goes high.

Design Gray Counter using VHDL Coding and Verify with Test Bench

Given below code is about Gray Counter in VHDL. In a gray code only one bit changes at a one time. This design code has two inputs clock and reset signals and one four bit output that will generate gray code. In the first if rst signal is high then output will be zero and as soon as rst will go low, on the rising edge of clk, design will generate four bit gray code and continue to generate at every rising edge of clk signal. This design code can be upgraded and put binary numbers as a input and this design will work as binary to gray code converter. Find out Verilog Code of Gray Counter here.

Design BCD to 7-Segment Decoder using Verilog Coding

Given below Verilog code will convert 4 bit BCD into equivalent seven segment number. It will accept 4 bit input and generate seven bit output. One seven segment can show zero to nine digit, so there is 4 bit input. Code is written for Common Cathode seven segment LED.So, LEDs will glow when the input is high. Find VHDL Code here.

Common Cathode Seven Segment Display

Design 4 bit Magnitude Comprator using Verilog and Verify with Test Bench

This design accepts two four bit inputs 'a' and 'b' and generates three one bit outputs 'eq', 'gt' and 'lt'. If both inputs are same then 'eq' bit will be high and other two outputs will be low. If 'a' is greater than 'b' then 'gt' will be high and other two outputs will be low. Same way if 'a' is less than 'b' then 'lt' output will go high and other two output will go low.

All About Operators in Verilog

Every language has its own set of Operators. VHDL has its own operators, same way Verilog has own set of operators to perform several operation on inputs. If you have knowledge of operators in C or C++, then it is very easy to understand operators in Verilog. There are total ten types of operators in Verilog. Operators are depending on number of operands.

• Arithmetic
• Relational
• Equality
• Logical
• Bit-wise
• Reduction
• Shift
• Concatenation
• Replication
• Conditional