Verilog Code for Sequence Detector "101101"

Here below verilog code for 6-Bit Sequence Detector "101101" is given. This code is implemented using FSM. FSM for this Sequence Detector is given in this image.

In this Sequence Detector, it will detect "101101" and it will give output as '1'.

VHDL Code for Bidirectional Bus

Here I have given a block diagram of Bidirectional Bus. This bus takes input from Data_in and gives output from Bi_Data when OE signal is high. In the same way when OE signal is low then it takes input from Bi_Data and gives output from Data_Out. Below I have mentioned input output into table.

Verilog Code for Johnson Counter

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find VHDL Code here.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

Verilog Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out VHDL Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

Features of Verilog Language

• Verilog is case sensitive.

• In verilog, Keywords are defined in lower case.

• In Verilog, Most of the syntax is adopted from "C" language.

• Verilog can be used to model a digital circuit at Algorithm, RTL, Gate and Switch level.

• There is no concept of package in Verilog.

• It also supports advanced simulation features like TEXTIO, PLI, and UDPs.