Verilog Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out VHDL Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

Features of Verilog Language

• Verilog is case sensitive.

• In verilog, Keywords are defined in lower case.

• In Verilog, Most of the syntax is adopted from "C" language.

• Verilog can be used to model a digital circuit at Algorithm, RTL, Gate and Switch level.

• There is no concept of package in Verilog.

• It also supports advanced simulation features like TEXTIO, PLI, and UDPs.

VHDL Programming Code Structure

VHDL stands for Very High speed integrated circuits Hardware Description Language. It was funded by the US Department of Defense in the 70’s and 80’s. It was established as IEEE standard IEEE 1076 in 1987. It was later updated on 1993, 2002 and 2008. Today VHDL is widely used across the industry for design description, simulation and synthesis purpose.

Here General Structure of VHDL Program is given below

·         Library Declaration

·         Package Declaration

·         User Defined Library Declaration*

·         User Defined Package Declaration*

·         Entity Declaration

o   Generic Declaration

o   Port Declaration

·         Architecture Declaration

·         Configuration Declaration

Setup Time and Hold Time

These two parameters are associated with Flip-Flop. Setup Time and Hold Time are two most important factors in Synchronous Design in VLSI Domain. If either of them is violated then Flip-Flop will not give proper output. 

Setup Time: - It’s a time interval before the Clock signal is triggered, where Data signal should be stable. So, that Data is easily sampled by the Flip-Flop.

Difference between Flip-Flop and Latch

Flip-Flop	Latch
Flip-Flop is Edge sensitive device.	Latch is Level sensitive device.
In Flip-Flop, output will change on rising or falling edge of clock signal.	In Latch, if Enable/Clock signal is high then output will change accordingly input.
So, we can say that Flip-Flop is a Synchronous version of Latch.	So, we can say that Latch is Asynchronous device.
Flip-Flop based design creates less timing problems.	Latch based design creates more timing problems.
In design Flip-Flop takes more area compared to Latch.	In design Latch takes less area compared to Flip-Flop.
In design Flip-Flop consumes more power compare to Latch.	In design Latch consumes less power compare to Flip-Flop.