Verilog Code for 4-Bit Sequential Multiplier Using Booths Algorithm

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	4	Data Input
2	b	Input	4	Data Input
3	Load	Input	1	Load Input
4	Rst_a	Input	1	Reset Input
5	Clk	Input	1	Clock Input
6	Op	Output	8	Multiplied Output

Verilog Code for 4-Bit Sequential Multiplier

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	4	Data Input
2	b	Input	4	Data Input
3	Load	Input	1	Load Input
4	Rst_a	Input	1	Reset Input
5	Clk	Input	1	Clock Input
6	Op	Output	8	Multiplied Output
7	Ready_out	Output	1	Ready_out Output

Sequential multiplier multiplies two inputs of four bits and gives output of eight bits. It also gives ready_out signal. It will give output in single cycle. It accepts data of a and b when load signal is high. If load signal is low, then it will not accept the data and output will not generated. It will generate multiplied output and ready_out signal high. 

Verilog Code for 8-Bit Universal Shifter

Sr. No.	Name of the Pin	Direction	Width	Description
1	ip	Input	8	data input
3	Rst_a	Input	1	Reset signal
4	Clk	Input	1	Clock signal
5	Sh_ro_lt_rt	Input	2	“00”=shift left “01”=shift right “10”=rotate left “11”=rotate right
6	load	Input	1	‘1’=receive input data ‘0’=display output of received data
7	op	Output	8	Parallel data output

module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);
  output reg [7:0] op;
  input load;
  input [1:0] sh_ro_lt_rt;
  input [7:0] ip;
  input clk, rst_a;


  reg [7:0]temp;

  always @(posedge clk or posedge rst_a)
   begin
     if (rst_a)
       op = 0;
     else  
       case(load)
         1'b1:
          begin                            //Load Input
            temp = ip;
          end
         1'b0:                             //Operation
          case (sh_ro_lt_rt)
            2'b00:  op = temp<<1;     //Left Shift
            2'b01:  op = temp>>1;     //Right Shift
            2'b10:  op = {temp[6:0],temp[7]}; //Rotate Left
            2'b11:  op = {temp[0], temp[7:1]};  //Rotate Right
            default: $display("Invalid Shift Control Input");
          endcase
   
       default: $display("Invalid Load Control Input");
       endcase
    end
endmodule

Verilog Code for 16x4 Memory

Sr. No.	Name of the Pin	Direction	Width	Description
1	Address	Input	4	Input address
2	Ip	input	4	Input data to memory
3	Rd_wr	Input	1	Control signal 1=read from memory 0=write in to memory
4	Clk	Input	1	Clock input
5	op	Output	4	Output read from memory

module memory_16x4(op,ip,rd_wr,clk,address);
   output reg [3:0] op;
   input [3:0]  ip;
   input [3:0] address;
   input  rd_wr,clk;
   reg [3:0]  memory[0:15];



   always @(posedge clk)
     begin
       if (rd_wr)
         op=memory[address];
       else
         begin
           memory[address]=ip;
       end
     end
endmodule // memory_16x4

Verilog Code for 16x4 Bi-Directional Port Memory

Sr. No.	Name of the Pin	Direction	Width	Description
1	address	Input	4	Input address i.e. address bus
2	out_en	input	1	output enable
3	rd_en	Input	1	If 1 read from memory
4	wr_en	Input	1	If 1 write in to memory
5	data	Input/Output	4	Output read/write from/to memory i.e. bidirectional data bus

module memory_16x4_bi(data, clk, out_en, address, rd_en, wr_en );
   inout [0:3] data;
   input clk;
   input out_en;
   input rd_en, wr_en;
   input [0:3] address;
   reg [0:3] memory [0:15];
   reg [0:3] data_out;



   assign data = out_en ? data_out : 4'bZ;
 
   always@(posedge clk)
     begin
      if(rd_en)
        data_out = memory[address];
      else if (wr_en)
        memory[address] = data;
      else
        data_out = 4'bx;
     end
 
endmodule