Test Bench for 4-bit Up-Down Counter in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity up_down_counter_tst is

end up_down_counter_tst;

architecture beh of up_down_counter_tst is

component up_down_counter
  port(clk, rst_a,mode : in std_logic;
      q : out std_logic_vector(3 downto 0));
end component;

signal clk_s,rst_a_s,mode_s : std_logic;
signal q_s : std_logic_vector(3 downto 0);

begin  -- beh

  u1 : up_down_counter port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    mode  => mode_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;

    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
   wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
  end process tst;

end beh;

VHDL Code for 4-bit Up-Down Counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_down_counter is

  port(clk, rst_a, mode : in std_logic;  --mode=1 up counting, mode=0 down counting
        q : out std_logic_vector(3 downto 0));

end up_down_counter;

architecture archi of up_down_counter is
  signal tmp: std_logic_vector(3 downto 0);
  begin
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
        elsif (clk'event and clk='1') then
          if (mode='1') then
            tmp <= tmp + 1;
          else
            tmp <= tmp - 1;
          end if;
        end if;
    end process;
    q <= tmp;
end archi;

Test Bench for Asynchronous Reset D-FlipFlop in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity dff_async_reset_tst is
 
end dff_async_reset_tst;

architecture beh of dff_async_reset_tst is
component dff_async_reset
  port (
    data, load, reset_a, clk, enb : in  std_logic;   -- inputs
    q                             : out std_logic);  -- output
end component;
  signal data_s,load_s,reset_a_s,clk_s,enb_s : std_logic := '0';
  signal q_s : std_logic;
begin  -- beh

  u1 : dff_async_reset port map (
    data    => data_s,
    load    => load_s,
    reset_a => reset_a_s,
    clk     => clk_s,
    enb     => enb_s,
    q       => q_s);

  tst_p: process
  begin  -- process tst_p
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process tst_p;

 dff: process
 begin  -- process dff
   reset_a_s <= '1';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '1';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '0';
   wait for 100 ns;
 
 end process dff;
end beh;

VHDL Code for Asynchronous Reset D-FlipFlop

library ieee;
use ieee.std_logic_1164.all;

  entity dff_async_reset is
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          enb     :in  std_logic;  -- enable pin
          load    :in  std_logic   -- load the input
      );
  end entity;

  architecture beh of dff_async_reset is

  begin
      process (clk,reset_a,enb,load)
           begin
         
          if (reset_a = '1') then
              q <= '0';
          elsif(rising_edge(clk) and enb ='1') then
              if(load = '1') then
                q <= '1';
              else
                q<= data;
              end if;          
          end if;
    end process;
end architecture;

Test Bench For 4-Bit Magnitude Comparator in VHDL

Find out VHDL code of Magnitude Comparator here.

library ieee;
use ieee.std_logic_1164.all;

entity mag_comp_4b_tst is
  
end mag_comp_4b_tst;

architecture beh of mag_comp_4b_tst is

component mag_comp_4b
  port (
    a, b : in  std_logic_vector(3 downto 0);                     -- inputs
    ag,bg,eq    : out std_logic);                    -- output
end component;
signal a_s,b_s : std_logic_vector(3 downto 0);
signal ag_s,bg_s,eq_s : std_logic;
  
begin  -- beh

  u1 : mag_comp_4b port map (
    a => a_s,
    b => b_s,
    ag => ag_s,
    eq => eq_s,
    bg => bg_s);
  tst_p:process
    begin
      a_s<="1111";
      b_s<="0000";
      wait for 100 ns;
       a_s<="1010";
      b_s<="1100";
      wait for 100 ns;
       a_s<="1001";
      b_s<="0011";
      wait for 100 ns;
       a_s<="1000";
      b_s<="1000";
      wait for 100 ns;

    end process;

end beh;

Simulated waveform of Magnitude Comparator is given below. This code is simulated using Xilinx Vivado.

Simulation Waveform of Magnitude Comparator