Verilog
|
VHDL
|
Verilog isn’t strongly typed language.
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VHDL is strongly typed language.
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Verilog is case sensitive language.
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VHDL is case insensitive language.
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Verilog is easy to learn comparatively VHDL.
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VHDL is hard to learn comparatively Verilog.
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Verilog has simple data types. |
VHDL allows creating more complex data types.
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Verilog has a lack of library management.
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VHDL has a very good library management.
|
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Showing posts with label Verilog. Show all posts
Showing posts with label Verilog. Show all posts
Wednesday 4 December 2013
Difference between Verilog and VHDL
Difference between Function and Task in Verilog
Function
|
Task
|
A Function must execute in one simulation time
unit.
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A Task may execute in non-zero simulation time.
|
A function can’t contain time-controlling event.
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A task can contain time-controlling event.
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A function can enable only function, not task.
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A task can enable function and task.
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A function must have at least one input argument.
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A task can have zero or more arguments of any
type.
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A function returns a single value that is of bit
or vector.
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A task doesn’t return a value.
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Thursday 7 November 2013
Design Round Robin Arbiter using Verilog FSM Coding with Variable Slice Period
Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
Clk
|
Input
|
1
|
Clock Signal
|
2
|
Rst
|
Input
|
1
|
Reset Signal
|
3
|
Req
|
Input
|
4
|
4 Request Signals
|
4
|
Grant
|
Output
|
4
|
4 Grant Signals
|
Round-robin (RR) is one of the simplest scheduling algorithms for processes in an operating system. As the term is generally used, time slices are assigned to each process in equal portions and in circular order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. In this Arbiter, we have included one two bit counter. This counter will count no. of clock pulses for grant period of each request signal. In this if in between of counter, the request signal goes low, then grant will be given to other respective request signal and we can save that time slice.
Verilog Code for Vending Machine Using FSM
Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
Nw_pa
|
Output
|
1
|
News Paper Signal
|
2
|
Coin
|
Input
|
2
|
Only two Coins,
5 =2’b01 10 =2’b10 0 =2’b00 |
3
|
Clk
|
Input
|
1
|
Clock Signal
|
4
|
Rst
|
Input
|
1
|
Reset Signal
|
In this wending machine, it accepts only two coins, 5 point and 10 point. Whenever total of coins equal to 15 points, then nw_pa signal will go high and user will get news paper. It will not return any coin, if total of points exceeds 15 points.
Design Traffic Light Controller using Verilog FSM Coding and Verify with Test Bench
Given below code is design code for Traffic Light Controller using Finite State Machine(FSM). In this clk and rst_a are two input signal and n_lights, s_lights, e_lights and w_lights are 3 bit output signal. In output signal, "001" represents Green light, "010" represents Yellow light and "100" represents Red light. On the reset signal, design will enter into north state and start giving output after reset will go low. Design will turn on Green light for eight clock cycles and Yellow light for four clock cycles. Design will start with north, then goes into south, then east and finally into west and by this it will keep going.
Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
n_lights
|
Output
|
3
|
North Lights
(001 = Green, 010 = Yellow, 100 = Red) |
2
|
s_lights
|
Output
|
3
|
South Lights
(001 = Green, 010 = Yellow, 100 = Red) |
3
|
e_lights
|
Output
|
3
|
Eight Lights
(001 = Green, 010 = Yellow, 100 = Red) |
4
|
w_lights
|
Output
|
3
|
West Lights
(001 = Green, 010 = Yellow, 100 = Red) |
5 | clk | Input | 1 | Clock Signal |
6
|
Rst_a
|
Input
|
1
|
Reset Signal
|
Verilog Code for Asynchronous Clear D-FlipFlop Using Primitive
Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
d
|
Input
|
1
|
Data input
|
2
|
clk
|
Input
|
1
|
Clock Signal
|
3
|
clear
|
Input
|
1
|
async clear Signal
|
4
|
q
|
Output
|
1
|
Data Output
|
Verilog Code for 4x1 Multiplexer Using Primitive
Sr. No.
|
Name of the Pin
|
Direction
|
Width
|
Description
|
1
|
Ip
|
Input
|
4
|
Input to be muxed
|
2
|
Sel
|
Input
|
2
|
Select Lines
|
3
|
Op
|
Output
|
1
|
Muxed Output
|
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