Difference between Verilog and VHDL

Verilog	VHDL
Verilog isn’t strongly typed language.	VHDL is strongly typed language.
Verilog is case sensitive language.	VHDL is case insensitive language.
Verilog is easy to learn comparatively VHDL.	VHDL is hard to learn comparatively Verilog.
Verilog has simple data types.	VHDL allows creating more complex data types.
Verilog has a lack of library management.	VHDL has a very good library management.