Design 4-bit Linear Feedback Shift Register (LFSR) using VHDL Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. It is used for State Encoding. It is also used to generate random numbers. Find out Verilog code here.

Excitation and Characteristic Table of SR Flip Flop

The basic SR Flip-Flop is shown below. The inputs, labeled S and R are used to SET and RESET the device, respectively. The outputs Q and Q’ are complementary. Because the Flip-Flop is unclocked, any change to the inputs will produce a change at the outputs. An invalid state occurs when both inputs are low; thus, the inputs should be kept high except when the Flip-Flop is to be set or cleared. Note that there are other implementations for a latch. Here we are showing a NAND implementation.

Design 8 bit Ripple Carry Adder using VHDL Coding and Verify using Test Bench

Given below code will generate 8 bit output as sum and 1 bit carry as cout.  it also takes two 8 bit inputs as a and b, and one input carry as cin. This code is implemented in VHDL by structural style. Predefined full adder code is mapped into this ripple carry adder. Full Adder code can be found here. Carry is generated by adding each bit of two inputs and propagated to next bit of inputs. If carry is generated by adding seventh bits and previous carry, then cout bit goes high.