All About Operators in Verilog

Every language has its own set of Operators. VHDL has its own operators, same way Verilog has own set of operators to perform several operation on inputs. If you have knowledge of operators in C or C++, then it is very easy to understand operators in Verilog. There are total ten types of operators in Verilog. Operators are depending on number of operands.

• Arithmetic
• Relational
• Equality
• Logical
• Bit-wise
• Reduction
• Shift
• Concatenation
• Replication
• Conditional

Quick Overview To Start Coding into Verilog

• Verilog is very popular Hardware Description language. It was introduced by Gateway Design Automation in 1984. In 1989, Cadence Design Systems purchased and put into public domain in 1990. In 1993, OVI enhanced the verilog language but that was not well accepted. IEEE standardized the Verilog HDL(IEEE 1364-1995) in 1995. In 2001, extension to verilog-95 submitted to IEEE and accepted verilog IEEE std 1364-2001. The revision of the language is also done in 2002 and 2005.

A Brief Overview Of Data Type in VHDL.

VHDL is strongly typed language and it supports a variety of Data Types and Operators. Users can also define their own data types and operators in user defined packages. There are three basic classes to define data objects in VHDL language.

• Signal : It represents interconnections that connect components and parts.
• Variable : It is used for local storage within process.
• Constant : It is used to declare a fixed value.

The data object can be a scalar or an array (one dimensional as well as multi dimensional).