Implement XOR Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Multiplexer's input to input 'B'. Connect input 'B' to input of NOT gate and output of this NOT gate connect to second input of Multiplexer. Then connect input 'A' to selection line of Multiplexer. So, this Multiplexer will XORing operation of input A, B.

Implement OR Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Mux's input to logic '1' and second to input 'B'. Connect input 'A' to selection line of Mux. So, output will give ORing operation of two inputs A, B.

Implement AND Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Mux's input to logic '0' and second to input 'B'. Connect input A to selection line of Mux. So, output of Mux will give anding operation of two inputs A and B.

Implement BUFFER Gate using XOR Gate

Connect one of XOR gate's input to logic '0' and connect second to input 'a'. So XOR gate will give output as input.

Implement NOT Gate using XOR Gate

Connect one of XOR gate's input to logic 1 and connect second input to input 'a'. So output of XOR gate will give inverted output of input.

Difference between $display and $strobe using Example in Verilog

Case 1 :

module case_1;
reg [31:0] data;

initial
 begin
  #20 data=50;
  $strobe("Strobe",$time,data);
  $display("display",$time,data);
  data=30;
 end

endmodule 

Ans. :

	Time	Data
$display	20	50
$strobe	20	30

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Interchange data without using third variable in Verilog

We can interchange value with the help of non-blocking statements.

always @ (a or b)

begin

a = 1;

b = 2;

#10;

Difference between Verilog and VHDL

Verilog	VHDL
Verilog isn’t strongly typed language.	VHDL is strongly typed language.
Verilog is case sensitive language.	VHDL is case insensitive language.
Verilog is easy to learn comparatively VHDL.	VHDL is hard to learn comparatively Verilog.
Verilog has simple data types.	VHDL allows creating more complex data types.
Verilog has a lack of library management.	VHDL has a very good library management.

Difference between Function and Task in Verilog

Function	Task
A Function must execute in one simulation time unit.	A Task may execute in non-zero simulation time.
A function can’t contain time-controlling event.	A task can contain time-controlling event.
A function can enable only function, not task.	A task can enable function and task.
A function must have at least one input argument.	A task can have zero or more arguments of any type.
A function returns a single value that is of bit or vector.	A task doesn’t return a value.