Verilog code to count number of 1's and 0's in 32-bit data input

There are many places where we need to check how many 0's or 1's are present in incoming data. It can be packet inspection or these counting further can be used for different purposes. This Verilog code is designed to efficiently count the occurrences of both '1' and '0' bits within a 32-bit input data. The primary objective of this module is to provide an accurate count of the number of '1's and '0's present in the input data simultaneously. Module takes 32-bit input data with valid bit. There are also clock and reset signals. Module has two output count vlaues, one for number of 1's and another one for number of 0's, and one valid signal. 32-bit input data is fed to the function only on valid_input and function will return number of 1's in the 32-bit data. This value will be subtracted from 32 and it will give us number of 0's present in the data. Both output values are true only when output_valid signal is high.

Rising and Falling Edge Detector using Verilog

 In the real word, there might be many scenario that we need to detect rising edge or falling edge of the signal. If rising/falling edge happens on particular signal, then design can perform certain task. This rising or falling edge can be detected using following code. This code is done in Verilog language. In given below example code, clock clk, input signal sig_a, output rising edge signal ris_a and falling edge signal fal_a are defined. Both ris_a and fal_a are high for one clock cycle when circuit detects rising or falling edge on the sig_a respectively.

Get Familiar with System Task in Verilog

There are special Tasks and Function in Verilog language which are used to generate input and output during simulation process. These special Tasks and Functions are always starts with $ sign, followed by Task/Function specifier. Synthesis tools ignore these system tasks and functions.

These System Tasks are classified as below

• Display Task
• $display, $write, $monitor, $strobe
• File I/O Task
• $fopen, $fclose, $fdisplay, $fstrobe, $fmonitor
• Timescale Task
• $time, $stime, $realtime
• Simulation Control Task
• $reset, $finish, $stop
  

Easy UVM (Universal Verification Methodology) Tutorial

UVM stands for Universal Verification Methodology. It is standard methodology to verify Integrated Circuits. UVM is derived from OVM, Open Verification Methodology. UVM is developed by Accellera with the support of Aldec, Cadence, Mentor Graphics and Synopsys. UVM is based on System Verilog language. With the help of UVM, engineers are able to create an efficient verification environment. It is portable from one project to another. Due to portability, engineers can reuse testbench from previous projects and modify different components as per their need. UVM easy tutorial is shown below. It is available on YouTube. It is developed by John Aynsley from Doulos. There are twenty videos. After watching this tutorial, overall picture of UVM will be cleared. 

Verilog Code for (7,4) Systematic Hamming Encoder

Hamming code is useful in Error Correction in Linear Block Code. This code will encode four bits of data and generate seven bits of code by adding three bits as parity bits. It was introduced by Richard W. Hamming. This algorithm can detect one and two bit error and can correct one bit error. Given below code will generate (7,4) Systematic Hamming Encoder. This encoder will use Least Significant 4 bits as data inputs and Most 3 significant bits as a parity bits.

Get VHDL Code.