Given below VHDL code will generate 1 kHz and 1 Hz frequency at the same time. This design takes 100 MHz as a input frequency. For this we need counter with different values and that will generate above frequencies. There is a simple formula to find this count value and it is given below.
Count Value = (Input Frequency) / (2 * Output Frequency).
In our case Count Value for 1 kHz is (100 * 10^6) / (2 * 1 * 10^3) = 50,000. After 50,000 count, level of msClk will change.
and for 1 Hz is (100 * 10^6) / (2 * 1) = 5,00,00,000.
Name of Pins
|
Direction
|
Data Width
|
sysClk
|
Input
|
1
|
msClk
|
Output
|
1
|
secClk
|
Output
|
1
|