Verilog Code for 16x4 Memory

Sr. No.	Name of the Pin	Direction	Width	Description
1	Address	Input	4	Input address
2	Ip	input	4	Input data to memory
3	Rd_wr	Input	1	Control signal 1=read from memory 0=write in to memory
4	Clk	Input	1	Clock input
5	op	Output	4	Output read from memory

module memory_16x4(op,ip,rd_wr,clk,address);
   output reg [3:0] op;
   input [3:0]  ip;
   input [3:0] address;
   input  rd_wr,clk;
   reg [3:0]  memory[0:15];



   always @(posedge clk)
     begin
       if (rd_wr)
         op=memory[address];
       else
         begin
           memory[address]=ip;
       end
     end
endmodule // memory_16x4

Verilog Code for 16x4 Bi-Directional Port Memory

Sr. No.	Name of the Pin	Direction	Width	Description
1	address	Input	4	Input address i.e. address bus
2	out_en	input	1	output enable
3	rd_en	Input	1	If 1 read from memory
4	wr_en	Input	1	If 1 write in to memory
5	data	Input/Output	4	Output read/write from/to memory i.e. bidirectional data bus

module memory_16x4_bi(data, clk, out_en, address, rd_en, wr_en );
   inout [0:3] data;
   input clk;
   input out_en;
   input rd_en, wr_en;
   input [0:3] address;
   reg [0:3] memory [0:15];
   reg [0:3] data_out;



   assign data = out_en ? data_out : 4'bZ;
 
   always@(posedge clk)
     begin
      if(rd_en)
        data_out = memory[address];
      else if (wr_en)
        memory[address] = data;
      else
        data_out = 4'bx;
     end
 
endmodule

Verilog Code for 8-Bit ALU

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	8	Data Input
2	b	Input	8	Data Input
3	opcode	Input	4	Control Logic for different operation
4	Op	Output	8	Output

There are total three inputs and one output signals. Two inputs a and b are input signals on which operation is going to be performed according to opcode input. a and b are 8 bit wide. opcode is 4 bit wide, so we can do sixteen different operations. The design code is given below. This is simple ALU. 

Design 8x3 Priority Encoder in Verilog Coding and Verify with TestBench

Priority Encoder allocates priority to each input. Design and Test Bench code of 8x3 Priority Encoder is given below. Output are set according to priorities of inputs. So if input with higher priority is present then inputs with lower priorities are ignored and generates output according to highest priority input.

S. No.	Name	Direction	Width	Remark
1.	D_in	IN	8 bit	Input lines
3.	D_out	OUT	3 bit	Output lines

Verilog Code for 4x16 Decoder

Sr. No.	Name of the Pin	Direction	Width	Description
1	D_in	Input	4	Input to be decoded
2	D_out	Output	16	Decoded output

module decoder_4x16 (d_out, d_in);

   output [15:0] d_out;
   input [3:0]   d_in;
   parameter tmp = 16'b0000_0000_0000_0001;

assign d_out = (d_in == 4'b0000) ? tmp   :
               (d_in == 4'b0001) ? tmp<<1:
               (d_in == 4'b0010) ? tmp<<2:
               (d_in == 4'b0011) ? tmp<<3:
               (d_in == 4'b0100) ? tmp<<4:
               (d_in == 4'b0101) ? tmp<<5:
               (d_in == 4'b0110) ? tmp<<6:
               (d_in == 4'b0111) ? tmp<<7:
               (d_in == 4'b1000) ? tmp<<8:
               (d_in == 4'b1001) ? tmp<<9:
               (d_in == 4'b1010) ? tmp<<10:
               (d_in == 4'b1011) ? tmp<<11:
               (d_in == 4'b1100) ? tmp<<12:
               (d_in == 4'b1101) ? tmp<<13:
               (d_in == 4'b1110) ? tmp<<14:
               (d_in == 4'b1111) ? tmp<<15: 16'bxxxx_xxxx_xxxx_xxxx;

endmodule