VHDL Code for 4-Bit Magnitude Comparator

Given below code is about 4-bit Magnitude comparator. First code is written using structural method and second code is written using behavioral method. This module has two 4-bit inputs 'a' and 'b' and three single bit output 'ag', bg' and 'eq'. In this code if 'a' is greater than 'b' then 'ag' will go high and rest will be low. Same way if 'b' is grater than 'a' then 'bg' will go high and rest will go low. If 'a' and 'b' are equal then 'eq' will go high and rest will go low. Find out Test Bench here.

Test Bench for Half Adder in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity half_adder_tst is
  
end half_adder_tst;
 architecture beh of half_adder_tst is
   component half_adder
       port (
    ip1,ip2: in  std_logic;   -- inputs
    sum,ca: out std_logic);  -- outputs

end component;
    signal ip1_s,ip2_s : std_logic;  -- signals
    signal sum_s,ca_s : std_logic;  -- output signals
 begin  -- beh

u1 : half_adder port map (
  ip1 => ip1_s,
   ip2 => ip2_s,
   sum => sum_s,
  ca => ca_s);

tst_p: process
   begin
      ip1_s<='0';
       ip2_s<='0';
       wait for 100 ns;
       ip1_s<='0';
       ip2_s<='1';
       wait for 100 ns;
       ip1_s<='1';
       ip2_s<='0';
       wait for 100 ns;
       ip1_s<='1';
       ip2_s<='1';
       wait for 100 ns;
    end process;
       
 end beh;

VHDL Code for Half-Adder

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is

  port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    sum : out std_logic;
    ca  : out std_logic);

end half_adder;

architecture half_adder_beh of half_adder is

begin  -- half_adder_beh

  sum <= ip1 xor ip2;
  ca <= ip1 and ip2;

end half_adder_beh;

Test Bench for 4-Bit Full Adder in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_4b_tst is
 
end full_adder_4b_tst;
 architecture beh of full_adder_4b_tst is
   component full_adder_4b
       port (
    a,b: in  std_logic_vector(3 downto 0);   -- inputs
     c :inout std_logic_vector(4 downto 1);  --carry out
    s: out std_logic_vector(3 downto 0));  -- outputs

end component;
    signal a_s,b_s : std_logic_vector(3 downto 0);  -- signals
    signal s_s : std_logic_vector(3 downto 0);  -- output signals
    signal c_s : std_logic_vector(4 downto 1);
 begin  -- beh

u1 : full_adder_4b port map (
  a => a_s,
   b => b_s,
   c => c_s,
   s => s_s);

tst_p: process
   begin
      a_s<="0000";
       b_s<="0101";
       wait for 100 ns;
       a_s<="1100";
       b_s<="0100";
       wait for 100 ns;
       a_s<="1111";
       b_s<="0000";
       wait for 100 ns;
       a_s<="0010";
       b_s<="1101";
       wait for 100 ns;
      end process;
  end beh;

VHDL Code for 4-bit Full-Adder

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_4b is

  port (
    a,b : in std_logic_vector(3 downto 0);
    s : out std_logic_vector(3 downto 0);
    c : inout std_logic_vector(4 downto 1)
    );
 
end full_adder_4b;

architecture beh of full_adder_4b is
constant c0 : std_logic := '0';         -- carry to the first full adder block
begin  -- beh

  s(0) <= a(0) xor b(0) xor c0;
  c(1) <= (a(0) and b(0))or(b(0) and c0)or(a(0) and c0);
  s(1) <= a(1) xor b(1) xor c(1);
  c(2) <= (a(1) and b(1))or(b(1) and c(1))or(a(1) and c(1));
  s(2) <= a(2) xor b(2) xor c(2);
  c(3) <= (a(2) and b(2))or(b(2) and c(2))or(a(2) and c(2));
  s(3) <= a(3) xor b(3) xor c(3);
  c(4) <= (a(3) and b(3))or(b(3) and c(3))or(a(3) and c(3));

end beh;