Verilog Code for Synchronous FIFO

Sr. No.	Name of the Pin	Direction	Width	Description
1	Rst_a	Input	1	Reset Input
2	Clk	Input	1	Clock Input
3	wr_en	Input	1	when high write into fifo
4	rd_en	input	1	when high read from memory
5	Data_in	Input	4	Data Input
6	Data_out	Output	4	Data output
7	Full	Output	1	Fifo status 1 if fifo is full
8	Empty	Output	1	Fifo status 1 if fifo is empty

module sync_fifo(data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en);
 
//---------------parametre declaration
   parameter data_width    = 4;
   parameter address_width = 4;
   parameter ram_depth     =16;



//--------------input output port declaration
   output [data_width-1:0] data_out;
   output      full;
   output      empty;
   input [data_width-1:0]  data_in;
   input      clk;
   input      rst_a;
   input      wr_en;
   input      rd_en;

//--------------internal register declaration
   reg [address_width-1:0]    wr_pointer;
   reg [address_width-1:0]    rd_pointer;
   reg [address_width :0]     status_count;
   reg [data_width-1:0]       data_out ;
   wire [data_width-1:0]      data_ram ;


 
//--------------wr_pointer pointing to write address
   always @ (posedge clk,posedge rst_a)
     begin
  if(rst_a)
   wr_pointer = 0;
  else
   if(wr_en)
    wr_pointer = wr_pointer+1;
 end
//-------------rd_pointer points to read address
   always @ (posedge clk,posedge rst_a)
     begin
  if(rst_a)
   rd_pointer = 0;
  else
   if(rd_en)
    rd_pointer = rd_pointer+1;
 end
//-------------read from FIFO
   always @ (posedge clk,posedge rst_a)
    begin
  if(rst_a)
   data_out=0;
  else
   if(rd_en)
    data_out=data_ram;
    end

//--------------Status pointer for full and empty checking
   always @ (posedge clk,posedge rst_a)
    begin
  if(rst_a)
   status_count = 0;
  else
   if(wr_en && !rd_en && (status_count != ram_depth))
    status_count = status_count + 1;
  else
   if(rd_en && !wr_en && (status_count != 0))
    status_count = status_count - 1;
    end // always @ (posedge clk,posedge rst_a)


   assign full = (status_count == (ram_depth));
   assign empty = (status_count == 0);
 
   memory_16x4 #(data_width,address_width,ram_depth) u1 

               (.address_1(wr_pointer),.address_2(rd_pointer),.data_1(data_in),.data_2(data_ram),.wr_en1(wr_en),.rd_en2(rd_en),.clk(clk));

endmodule // sync_fifo

Verilog Code for 4-Bit Sequential Multiplier Using Booths Algorithm

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	4	Data Input
2	b	Input	4	Data Input
3	Load	Input	1	Load Input
4	Rst_a	Input	1	Reset Input
5	Clk	Input	1	Clock Input
6	Op	Output	8	Multiplied Output

Verilog Code for 4-Bit Sequential Multiplier

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	4	Data Input
2	b	Input	4	Data Input
3	Load	Input	1	Load Input
4	Rst_a	Input	1	Reset Input
5	Clk	Input	1	Clock Input
6	Op	Output	8	Multiplied Output
7	Ready_out	Output	1	Ready_out Output

Sequential multiplier multiplies two inputs of four bits and gives output of eight bits. It also gives ready_out signal. It will give output in single cycle. It accepts data of a and b when load signal is high. If load signal is low, then it will not accept the data and output will not generated. It will generate multiplied output and ready_out signal high. 

Verilog Code for 8-Bit Universal Shifter

Sr. No.	Name of the Pin	Direction	Width	Description
1	ip	Input	8	data input
3	Rst_a	Input	1	Reset signal
4	Clk	Input	1	Clock signal
5	Sh_ro_lt_rt	Input	2	“00”=shift left “01”=shift right “10”=rotate left “11”=rotate right
6	load	Input	1	‘1’=receive input data ‘0’=display output of received data
7	op	Output	8	Parallel data output

module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);
  output reg [7:0] op;
  input load;
  input [1:0] sh_ro_lt_rt;
  input [7:0] ip;
  input clk, rst_a;


  reg [7:0]temp;

  always @(posedge clk or posedge rst_a)
   begin
     if (rst_a)
       op = 0;
     else  
       case(load)
         1'b1:
          begin                            //Load Input
            temp = ip;
          end
         1'b0:                             //Operation
          case (sh_ro_lt_rt)
            2'b00:  op = temp<<1;     //Left Shift
            2'b01:  op = temp>>1;     //Right Shift
            2'b10:  op = {temp[6:0],temp[7]}; //Rotate Left
            2'b11:  op = {temp[0], temp[7:1]};  //Rotate Right
            default: $display("Invalid Shift Control Input");
          endcase
   
       default: $display("Invalid Load Control Input");
       endcase
    end
endmodule