These two parameters are associated with Flip-Flop. Setup Time and Hold Time are two most important factors in Synchronous Design in VLSI Domain. If either of them is violated then Flip-Flop will not give proper output.
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Thursday 29 May 2014
Setup Time and Hold Time
Sunday 25 May 2014
Difference between Flip-Flop and Latch
Flip-Flop
|
Latch
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Flip-Flop is Edge sensitive device.
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Latch is Level sensitive device.
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In Flip-Flop, output will change on rising or
falling edge of clock signal.
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In Latch, if Enable/Clock signal is high then
output will change accordingly input.
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So, we can say that Flip-Flop is a Synchronous version of Latch.
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So, we can say that Latch is Asynchronous device.
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Flip-Flop based design creates less timing
problems.
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Latch based design creates more timing problems.
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In design Flip-Flop takes more area compared to
Latch.
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In design Latch takes less area compared to
Flip-Flop.
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In design Flip-Flop consumes more power compare
to Latch.
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In design Latch consumes less power compare to Flip-Flop.
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Wednesday 14 May 2014
Shift Operators in VHDL
There are total six shifting operators in VHDL language.
- sll
- It means Logical Shift Left.
- It shifts the elements in the array by n places to left and fill vacanted positions with "0".
- Ex
- "1000_1010" sll 3 will give "0101_0000".
- "1000_1010" sll -2 will give "0010_0010".
Wednesday 11 December 2013
Implement XOR Gate using 2x1 Multiplexer
We have two inputs A, B. Connect one of Multiplexer's input to input 'B'. Connect input 'B' to input of NOT gate and output of this NOT gate connect to second input of Multiplexer. Then connect input 'A' to selection line of Multiplexer. So, this Multiplexer will XORing operation of input A, B.
Monday 9 December 2013
Implement OR Gate using 2x1 Multiplexer
We have two inputs A, B. Connect one of Mux's input to logic '1' and second to input 'B'. Connect input 'A' to selection line of Mux. So, output will give ORing operation of two inputs A, B.
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