Get Familiar with System Task in Verilog

There are special Tasks and Function in Verilog language which are used to generate input and output during simulation process. These special Tasks and Functions are always starts with $ sign, followed by Task/Function specifier. Synthesis tools ignore these system tasks and functions.

These System Tasks are classified as below

• Display Task
• $display, $write, $monitor, $strobe
• File I/O Task
• $fopen, $fclose, $fdisplay, $fstrobe, $fmonitor
• Timescale Task
• $time, $stime, $realtime
• Simulation Control Task
• $reset, $finish, $stop
  

Easy UVM (Universal Verification Methodology) Tutorial

UVM stands for Universal Verification Methodology. It is standard methodology to verify Integrated Circuits. UVM is derived from OVM, Open Verification Methodology. UVM is developed by Accellera with the support of Aldec, Cadence, Mentor Graphics and Synopsys. UVM is based on System Verilog language. With the help of UVM, engineers are able to create an efficient verification environment. It is portable from one project to another. Due to portability, engineers can reuse testbench from previous projects and modify different components as per their need. UVM easy tutorial is shown below. It is available on YouTube. It is developed by John Aynsley from Doulos. There are twenty videos. After watching this tutorial, overall picture of UVM will be cleared.